參數(shù)資料
型號: ATF1508ASV-15QI100
廠商: Atmel
文件頁數(shù): 26/28頁
文件大?。?/td> 0K
描述: IC CPLD 15NS LOW V 100PQFP
標準包裝: 66
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 128
輸入/輸出數(shù): 80
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-BQFP
供應商設備封裝: 100-PQFP(14x20)
包裝: 托盤
其它名稱: ATF1508ASV15QI100
7
ATF1508ASV(L)
1408H–PLD–7/05
Programmable Pin-
keeper Option for
Inputs and I/Os
The ATF1508ASV(L) offers the option of programming all input and I/O pins so that “pin-
keeper” circuits can be utilized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Input Diagram
Speed/Power
Management
The ATF1508ASV(L) has several built-in speed and power management features. The
ATF1508ASV(L) contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power-savings for most
applications running at system speeds below 5 MHz.
To further reduce power, each ATF1508ASV(L) macrocell has a reduced-power bit fea-
ture. This feature allows individual macrocells to be configured for maximum power-
savings. This feature may be selected as a design option.
I/O Diagram
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