參數(shù)資料
型號(hào)： ATF1508ASL-25QI160
廠商： Atmel
文件頁(yè)數(shù)： 31/31頁(yè)
文件大小： 0K
描述： IC CPLD 25NS LOW PWR 160PQFP
標(biāo)準(zhǔn)包裝： 24
系列： ATF15xx
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 25.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 96
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤(pán)
其它名稱： ATF1508ASL25QI160
9
ATF1508AS(L)
0784P–PLD–7/05
ISP
Programming
Protection
The ATF1508AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition the pin-keeper option preserves the
former state during device programming.
All ATF1508AS devices are initially shipped in the erased state thereby making them ready to
use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
JTAG-BST
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1508AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The
ATF1508AS does not currently include a Test Reset (TRST) input pin because the TAP con-
troller is automatically reset at power-up. The six JTAG BST modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the ATF1508AS is imple-
mented using the Boundary-scan Definition Language (BSDL) described in the JTAG
specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can
be used to perform BST on the ATF1508AS.
The ATF1508AS also has the option of using four JTAG-standard I/O pins for In-System pro-
gramming (ISP). The ATF1508AS is programmable through the four JTAG pins using
programming compatible with the IEEE JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG
Boundary-scan
Cell (BSC)
Testing
The ATF1508AS contains up to 96 I/O pins and four input pins, depending on the device type
and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)
in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A
typical BSC consists of three capture registers or scan registers and up to two update regis-
ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the (BST) capture registers. Input to the cap-
ture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by
the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are
shown below.
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