參數(shù)資料
型號(hào)： ATF1502ASV-15JU44
廠商： Atmel
文件頁(yè)數(shù)： 23/25頁(yè)
文件大小： 0K
描述： IC CPLD EE HP 15NS 44-PLCC
標(biāo)準(zhǔn)包裝： 27
系列： ATF15xx
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 15.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 32
輸入/輸出數(shù)： 32
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC
包裝： 管件
產(chǎn)品目錄頁(yè)面： 608 (CN2011-ZH PDF)
配用： ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
7
1615J–PLD–01/06
ATF1502ASV
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-
rocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins, with
reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned
on), the reduced-power adder, t
RPA, must be added to the AC parameters, which include the
data paths t
LAD, tLAC, tIC, tACL, tACH and tSEXP.
The ATF1502ASV macrocell also has an option whereby the power can be reduced on a per-
macrocell basis. By enabling this power-down option, macrocells that are not used in an applica-
tion can be turned down, thereby reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
4.
Power-up Reset
The ATF1502ASV is designed with a power-up reset, a feature critical for state machine initial-
ization. At a point delayed slightly from V
CC crossing VRST, all registers will be initialized, and the
state of each output will depend on the polarity of its buffer. However, due to the asynchronous
nature of reset and uncertainty of how V
CC actually rises in the system, the following conditions
are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3.
The clock must remain stable during T
D.
The ATF1502ASV has two options for the hysteresis about the reset level, V
RST, Small and
Large. To ensure a robust operating environment in applications where the device is operated
near 3.0V, Atmel recommends that during the fitting process users configure the device with the
Power-up Reset hysteresis set to Large. For conversions, Atmel POF2JED users should include
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is added:
4.
If V
CC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, I
CC is reduced by several hundred microamps as
well.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1502ASV fuse patterns.
Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains
accessible.
6.
Programming
ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG proto-
col. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
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ATF1502ASV-20AI44 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL ISP STD PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF1502ASV-20JC44 功能描述:CPLD - 復(fù)雜可編程邏輯器件 ASICS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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