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參數(shù)資料
| 型號： | ATA6661-TAQJ 19 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX LIN 2.0 3.3V/5V 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | LIN |
| 電源電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
10
4729M–AUTO–02/09
ATA6661
6.3
Wake pull-up current
VS < 27V
3
IWAKE
–30
–10
A
6.4
High level leakage current
VS = 27V, VWAKE = 27V
3
IWAKE
–5
+5
A
7
LIN Bus Driver
7.1
Driver recessive output voltage
R
LOAD = 500Ω/1 kΩ
6V
BUSrec
0.9
×
V
S
V
S
VA
7.2
Driver dominant voltage
V
BUSdom_DRV_LoSUP
VVS = 7V, Rload = 500Ω
6V_LoSUP
1.2
V
A
7.3
Driver dominant voltage
VBUSdom_DRV_HiSUP
V
VS = 18V, Rload = 500Ω
6V
_HiSUP
2V
A
7.4
Driver dominant voltage
V
BUSdom_DRV_LoSUP
V
VS = 7V, Rload = 1000Ω
6V
_LoSUP_1k
0.6
V
A
7.5
Driver dominant voltage
V
BUSdom_DRV_HiSUP
VVS = 18V, Rload = 1000Ω
6V_HiSUP_1k_
0.8
V
A
7.6
Pull-up resistor to V
S
The serial diode is
mandatory
6R
LIN
20
30
60
k
Ω
A
7.7
Self-adapting current limitation
VBUS = VBAT_max
Tj = 125°C
T
j = 27°C
T
j = –40°C
6I
BUS_LIM
52
100
150
110
170
230
mA
A
7.8
Input leakage current at the
receiver, inclusive pull-up
resistor as specified
Input leakage current
Driver off
V
BUS = 0V, VBatt = 12V
6IBUS_PAS_dom
–1
mA
A
7.9
Leakage current LIN recessive
Driver off
8V < VBAT < 18V
8V < VBUS < 18V
V
BUS ≥ VBAT
6I
BUS_PAS_rec
15
20
A
7.10
Leakage current at ground loss,
Control unit disconnected from
ground,
Loss of local ground must not
affect communication in the
residual network
GND
Device = VS
VBAT =12V
0V < VBUS < 18V
6IBUS_NO_gnd
–10
+0.5
+10
A
7.11
Node has to sustain the current
that can flow under this
condition, bus must remain
operational under this condition
VBAT disconnected
VSUP_Device = GND
0V < V
BUS < 18V
6IBUS
0.5
3
A
8
LIN Bus Receiver
8.1
Center of receiver threshold
VBUS_CNT =
(V
th_dom + Vth_rec)/2
6VBUS_CNT
0.475
×
V
S
0.5
×
V
S
0.525
× V
S
VA
8.2
Receiver dominant state
VEN = 5V
6
VBUSdom
–27
0.4
×
VS
VA
8.3
Receiver recessive state
V
EN = 5V
6
V
BUSrec
0.6
×
V
S
40
V
A
8.4
Receiver input hysteresis
VHYS = Vth_rec – Vth_dom
6VBUShys
0.028
×
V
S
0.1
×
V
S
0.175
× V
S
VA
8.5
Wake detection LIN
High level input voltage
6V
LINH
V
S –
1V
V
S +
0.3V
VA
6.
Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to +125°C
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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