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參數(shù)資料
型號: AT91SAM9G20B-CFU
廠商: Atmel
文件頁數(shù): 12/42頁
文件大?。?/td> 0K
描述: IC MCU ARM9 247-LFBGA
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 240
系列: SAM9G
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 400MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,ISI,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 1.1 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 247-TFBGA
包裝: 托盤
2
6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
One 4-channel 10-bit Analog-to-Digital Converter
Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– All I/O Lines are Schmitt Trigger Inputs
Peripheral DMA Controller Channels (PDC)
One Two-slot MultiMedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– IS Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
Two 2-wire UARTs
Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
One Two-wire Interface (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
– Sequential Read/Write Operations
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave Mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode
IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies
– 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL
– 1.65 to 3.6V for VDDOSC
– 1.65V to 3.6V for VDDIOP (Peripheral I/Os)
– 3.0V to 3.6V for VDDUSB
– 3.0V to 3.6V VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
Available in a 217-ball LFBGA and 247-ball TFBGA RoHS-compliant Package
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