![](http://datasheet.mmic.net.cn/Atmel/AT91SAM9261SB-CU-999_datasheet_96507/AT91SAM9261SB-CU-999_658.png)
658
6242E–ATARM–11-Sep09
AT91SAM9261S
SDRAMC
15
CAS Low before SDCK Rising Edge
tCPSDCK/2 -
0.4
tCPSDCK/2 -
0.2
ns
SDRAMC
16
CAS High after SDCK Rising Edge
tCPSDCK/2 -
0.3
tCPSDCK/2 -
0.3
ns
SDRAMC17
DQM Change before SDCK Rising Edge
t
CPSDCK/2 -
3.4
t
CPSDCK/2 -
3.3
ns
SDRAMC18
DQM Change after SDCK Rising Edge
tCPSDCK/2 -
0.5
tCPSDCK/2 -
0.5
ns
SDRAMC19
D0-D15 in Setup before SDCK Rising Edge
1.4
ns
SDRAMC20
D0-D15 in Hold after SDCK Rising Edge
0.1
0.0
ns
SDRAMC
21
D16-D31 in Setup before SDCK Rising Edge
1.8
ns
SDRAMC22
D16-D31 in Hold after SDCK Rising Edge
0.0
ns
SDRAMC23
SDWE Low before SDCK Rising Edge
tCPSDCK/2 -
0.2
tCPSDCK/2 -
0.1
ns
SDRAMC
24
SDWE High after SDCK Rising Edge
tCPSDCK/2 -
0.4
tCPSDCK/2 -
0.4
ns
SDRAMC25
D0-D15 Out Valid before SDCK Rising Edge
t
CPSDCK/2 -
1.3
t
CPSDCK/2 -
1.1
ns
SDRAMC26
D0-D15 Out Valid after SDCK Rising Edge
t
CPSDCK/2 -
0.6
t
CPSDCK/2 -
0.6
ns
SDRAMC
27
D16-D31 Out Valid before SDCK Rising Edge
tCPSDCK/2 -
3.9
tCPSDCK/2 -
3.9
ns
SDRAMC
28
D16-D31 Out Valid after SDCK Rising Edge
t
CPSDCK/2 -
0.5
t
CPSDCK/2 -
0.5
ns
Table 39-22. SDRAM Signals (Continued)
Symbol
Parameter
Min
Units
1.8V
Supply
3.3V
Supply