參數(shù)資料
型號(hào): AT91SAM9260B-CU
廠商: Atmel
文件頁(yè)數(shù): 7/45頁(yè)
文件大?。?/td> 0K
描述: IC ARM9 MCU 217-LFBGA
產(chǎn)品培訓(xùn)模塊: SAM9 MPU Boot Solutions & Application Deployment
MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 126
系列: AT91SAM
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 180MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: ROM
RAM 容量: 24K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 217-LFBGA
包裝: 托盤(pán)
配用: AT91SAM9260-EK-ND - KIT EVAL FOR AT91SAM9260
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
15
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
7.
Processor and Architecture
7.1
ARM926EJ-S Processor
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
Two Instruction Sets
ARM High-performance 32-bit Instruction Set
Thumb High Code Density 16-bit Instruction Set
DSP Instruction Extensions
5-Stage Pipeline Architecture:
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Data Memory (M)
Register Write (W)
8-Kbyte Data Cache, 8-Kbyte Instruction Cache
Virtually-addressed 4-way Associative Cache
Eight words per line
Write-through and Write-back Operation
Pseudo-random or Round-robin Replacement
Write Buffer
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
Access Permission for Sections
Access Permission for large pages and small pages can be specified separately for each quarter of the
page
16 embedded domains
Bus Interface Unit (BIU)
Arbitrates and Schedules AHB Requests
Separate Masters for both instruction and data access providing complete Matrix system flexibility
Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
7.2
Bus Matrix
6-layer Matrix, handling requests from 6 masters
Programmable Arbitration strategy
Fixed-priority Arbitration
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
Burst Management
Breaking with Slot Cycle Limit Support
Undefined Burst Length Support
One Address Decoder provided per Master
Three different slaves may be assigned to each decoded memory area: one for internal boot, one for
external boot, one after remap
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