參數(shù)資料
型號(hào)： AT91SAM7S32B-AU
廠商： Atmel
文件頁數(shù)： 3/165頁
文件大?。?/td> 0K
描述： IC MCU ARM7 32KB FLASH 48LQFP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 250
系列： SAM7S
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 55MHz
連通性： I²C，SPI，SSC，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-LQFP
包裝： 托盤
配用： AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
100
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status
register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and
include:
the size of the request (field ABTSZ)
the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit
MISADD)
the source of the access leading to the last abort (bits MST0 and MST1)
whether or not an abort occurred for each master since the last read of the register (bit SVMST0 and SVMST1)
unless this information is loaded in MST bits
In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as search-
ing for which address generated the abort would require disassembling the instructions and full knowledge of the
processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM pro-
cessor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is
probable that several aborts have occurred during this time. Thus, in this case, it is preferable to use the content of
the Abort Link register of the ARM processor.
18.3.5
Embedded Flash Controller
The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the Flash block
with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buf-
fers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of
commands.
18.3.6
Misalignment Detector
The Memory Controller features a Misalignment Detector that checks the consistency of the accesses.
For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are
checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-
word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the
accesses of the ARM processor when it is fetching instructions are not checked.
The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particu-
larly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status Register and the address of the instruction generating the
misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bug is
simplified.
18.4
Memory Controller (MC) User Interface
Base Address: 0xFFFFFF00
Table 18-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
MC Remap Control Register
MC_RCR
Write-only
0x04
MC Abort Status Register
MC_ASR
Read-only
0x0
0x08
MC Abort Address Status Register
MC_AASR
Read-only
0x0
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