參數(shù)資料
型號: AT91RM9200-EK
廠商: Atmel
文件頁數(shù): 10/41頁
文件大小: 0K
描述: DEVEL KIT
標準包裝: 1
系列: ARM®, Thumb®
類型: MCU
適用于相關產(chǎn)品: ARM920T
所含物品: 開發(fā)板,AC 適配器,線纜以及軟件
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
其它名稱: Q2427672
18
1768MS–ATARM–09-Jul-09
AT91RM9200
A first level of address decoding is performed by the Memory Controller, i.e., by the implementa-
tion of the Advanced System Bus (ASB) with additional features.
Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are
directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The
area 0 is reserved for the addressing of the internal memories, and a second level of decoding
provides 1M bytes of internal memory area. The area 15 is reserved for the peripherals and pro-
vides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
8.1
Embedded Memories
8.1.1
Internal Memory Mapping
8.1.1.1
Internal RAM
The AT91RM9200 integrates a high-speed, 16-Kbyte internal SRAM. After reset and until the
Remap Command is performed, the SRAM is only accessible at address 0x20 0000. After
Remap, the SRAM is also available at address 0x0.
8.1.1.2
Internal ROM
The AT91RM9200 integrates a 128-Kbyte Internal ROM. At any time, the ROM is mapped at
address 0x10 0000. It is also accessible at address 0x0 after reset and before the Remap Com-
mand if the BMS is tied high during reset.
8.1.1.3
USB Host Port
The AT91RM9200 integrates a USB Host Port Open Host Controller Interface (OHCI). The reg-
isters of this interface are directly accessible on the ASB Bus and are mapped like a standard
internal memory at address 0x30 0000.
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