參數資料
型號: AT90USB1286-MUR
廠商: Atmel
文件頁數: 34/106頁
文件大?。?/td> 0K
描述: MCU AVR 128K FLASH 16MHZ 64QFN
產品培訓模塊: MCU Product Line Introduction
megaAVR Introduction
標準包裝: 4,000
系列: AVR® 90USB
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART,USB,USB OTG
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 48
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數據轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: AT90USB1286-MUR-ND
AT90USB1286-MURTR
33
7593L–AVR–09/12
AT90USB64/128
6.5.4
Pull-up and bus-keeper
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in “XMCRB – External Memory Control Register B”
on page 36. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
these lines are tri-stated by the XMEM interface.
6.5.5
Timing
External Memory devices have different timing requirements. To meet these requirements, the
XMEM interface provides four different wait-states as shown in Table 6-5 on page 36. It is impor-
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the setup requirement. The access time for the External Memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data is stable
during a read sequence (see t
LLRL+ tRLRH - tDVRH in Tables 31-6 through Tables 31-13 on pages
399 - 401). The different wait-states are set up in software. As an additional feature, it is possible
to divide the external memory space in two sectors with individual wait-state settings. This
makes it possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to Tables 31-6
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 6-6.
External data memory cycles without wait-state (SRWn1=0 and SRWn0=0).
ALE
T1
T2
T3
Wr
ite
Re
a
d
WR
T4
A15:8
Address
Prev. addr.
DA7:0
Address
Data
Prev. data
XX
RD
DA7:0 (XMBK = 0)
Data
Prev. data
Address
Data
Prev. data
Address
DA7:0 (XMBK = 1)
System Clock (CLKCPU)
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