參數(shù)資料
型號(hào): AT90S8515-8AC
廠商: Atmel
文件頁數(shù): 64/112頁
文件大?。?/td> 0K
描述: IC MCU 8K FLSH 8MHZ 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(4K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-TQFP
包裝: 托盤
55
AT90S8515
0841G–09/01
UART Control
UART I/O Data Register – UDR
The UDR register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data register is written. When
reading from UDR, the UART Receive Data register is read.
UART Status Register – USR
The USR register is a read-only register providing information on the UART status.
Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift reg-
ister to UDR. The bit is set regardless of any detected framing errors. When the RXCIE
bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is
set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used,
the UART Receive Complete Interrupt routine must read UDR in order to clear RXC,
otherwise a new interrupt will occur once the interrupt routine terminates.
Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift register has been shifted out and no new data has been written to UDR. This flag is
especially useful in half-duplex communications interfaces, where a transmitting appli-
cation must enter receive mode and free the communications bus immediately after
completing the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete
interrupt to be executed. TXC is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical
“1” to the bit.
Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift
register. Setting of this bit indicates that the transmitter is ready to receive a new charac-
ter for transmission.
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe-
cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven
data transmittal is used, the UART Data Register Empty Interrupt routine must write
UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou-
tine terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-
ing character is zero.
Bit
765
432
10
$0C ($2C)
MSB
LSB
UDR
Read/Write
R/W
Initial Value
0
Bit
765
432
10
$0B ($2B)
RXC
TXC
UDRE
FE
OR
USR
Read/Write
R
R/W
R
Initial Value
0
1
0
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AT90S8515-8JI 功能描述:8位微控制器 -MCU 8K Flash 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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AT90S8515-8PI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes In-System Programmable Flash