參數資料
型號: AT89LP4052-20SU
廠商: Atmel
文件頁數: 44/94頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 4K 20SOIC
產品培訓模塊: MCU Product Line Introduction
標準包裝: 38
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 15
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
產品目錄頁面: 616 (CN2011-ZH PDF)
49
3547J–MICRO–10/09
AT89LP2052/LP4052
20. Analog Comparator
A single analog comparator is provided on the AT89LP2052/LP4052. Comparator operation is
such that the output is a logic “1” when the positive input AIN0 (P1.0) is greater than the negative
input AIN1 (P1.1). Otherwise, the output is a zero. Setting the CEN bit in ACSR enables the
comparator. When the comparator is first enabled, the comparator output and interrupt flag are
guaranteed to be stable only after 10 s. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the interrupt
is enabled in order to prevent an immediate interrupt service. Before enabling the comparator
the analog inputs should be tri-stated by putting P1.0 and P1.1 into input-only mode. See Sec-
The comparator output is internally tied to the P3.6 pin. Instructions which read the pins of P3
will also read the comparator output directly. Read-Modify-Write instructions or Write instructions
to P3.6 will access bit 6 of the Port 3 register without affecting the comparator.
The comparator may be configured to cause an interrupt under a variety of output value condi-
tions by setting the CM bits in ACSR. The comparator interrupt flag CF in ACSR is set whenever
the comparator output matches the condition specified by CM. The flag may be polled by soft-
ware or may be used to generate an interrupt and must be cleared by software. The EC bit in IE
must be set before CF will generate an interrupt.
20.1
Comparator Interrupt with Debouncing
The comparator output is sampled every clock cycle. The conditions on the analog inputs may
be such that the comparator output will toggle excessively. This is especially true if applying slow
moving analog inputs. Three debouncing modes are provided to filter out this noise. In debounc-
ing mode, the comparator uses Timer 1 to modulate its sampling time. When a relevant
transition occurs, the comparator waits until two Timer 1 overflows have occurred before resam-
pling the output. If the new sample agrees with the expected value, CF is set. Otherwise the
event is ignored. The filter may be tuned by adjusting the time-out period of Timer 1. Because
Timer 1 is free running, the debouncer must wait for two overflows to guarantee that the sam-
pling delay is at least 1 time-out period. Therefore after the initial edge event, the interrupt may
occur between 1 and 2 time-out periods later. See Figure 20-1.
By default the comparator is disabled during Idle mode. To allow the comparator to function dur-
ing Idle, the CIDL bit in ACSR must be set. When CIDL is set, the comparator can be used to
wake-up the CPU from Idle if the comparator interrupt is enabled. The comparator is always dis-
abled during Power-down mode.
Figure 20-1. Negative Edge with Debouncing Example
Comparator Out
Timer 1 Overflow
CF
Start
Compare
Start
Compare
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