參數(shù)資料
型號: AT89LP213-20XU
廠商: Atmel
文件頁數(shù): 31/98頁
文件大?。?/td> 0K
描述: MCU 8051 2K FLASH 20MHZ 14-TSSOP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 95
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
37
3538E–MICRO–11/10
AT89LP213/214
15. External Interrupts
When the AT89LP213/214 is configured to use the internal RC Oscillator, XTAL1 and XTAL2
may be used as the INT0 and INT1 external interrupt sources. When the external clock source is
used, XTAL2 is available as INT1. Neither interrupt is available in crystal oscillator mode. The
external interrupts can be programmed to be level-activated or transition-activated by setting or
clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected
low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive
samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request
flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins
are sampled once each clock cycle, an input high or low should hold for at least 2 oscillator peri-
ods to ensure sampling. If the external interrupt is transition-activated, the external source has to
hold the request pin high for at least two clock cycles, and then hold it low for at least two clock
cycles to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be
automatically cleared by the CPU when the service routine is called if generated in edge-trig-
gered mode. If the external interrupt is level-activated, the external source has to hold the
request active until the requested interrupt is actually generated. Then the external source must
deactivate the request before the interrupt service routine is completed, or else another interrupt
will be generated.
16. General-purpose Interrupts
The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on
Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register
select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS regis-
ters determine the mode for each individual pin. GPMOD selects between level-sensitive and
edge-triggered mode. GPLS selects between high/low in level mode and positive/negative in
edge mode. The pins of Port 1 are sampled every clock cycle. In level-sensitive mode, a valid
level must appear in two successive samples before generating the interrupt. In edge-triggered
mode, a transition will be detected if the value changes from one sample to the next. When an
interrupt condition on a pin is detected, and that pin is enabled, the appropriate flag in the GPIF
register is set. The flags in GPIF must be cleared by software.
.
Table 16-1.
GPMOD
– General-purpose Interrupt Mode Register
GPMOD = 9AH
Reset Value = 0000 0000B
Not Bit Addressable
GPMOD7
GPMOD6
GPMOD5
GPMOD4
GPMOD3
GPMOD2
GPMOD1
GPMOD0
Bit
7
6
543
21
0
GPMOD.x
0 = level-sensitive interrupt for P1.x
1 = edge-triggered interrupt for P1.x
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