參數(shù)資料
型號(hào): AT89C51RC-24PU
廠商: Atmel
文件頁(yè)數(shù): 6/36頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32K FLASH 24MHZ 40-DIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 10
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: SPI,UART/USART
外圍設(shè)備: WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
配用: AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
14
1920D–MICRO–6/08
AT89C51RC
13.2
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload
mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR
T2MOD (see Table 13-2). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to
count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the
T2EX pin.
Figure 13-2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options
are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets
the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the
16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and
RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit.
Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 13-2. In this
mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count
up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit
value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2,
respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal
the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH
to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit
of resolution. In this operating mode, EXF2 does not flag an interrupt.
Figure 13-1. Timer in Capture Mode
OSC
EXF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CONTROL
CAPTURE
OVERFLOW
CONTROL
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
÷12
RCAP2L
RCAP2H
TH2
TL2
TF2
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