81
AT89C51RB2/RC2
4180E–8051–10/06
Table 1. Minimum Reset Capacitor Value for a 50 k
Ω Pull-down Resistor(1)
Note:
These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Reset
clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 k
Ω
Figure 33. Reset Circuitry for WDT Reset-out Usage
Oscillator
Start-Up Time
VDD Rise Time
1 ms
10 ms
100 ms
5 ms
820 nF
1.2 F
12 F
20 ms
2.7 F
3.9 F
12 F
R
RS
T
RST
VSS
To CPU Core
and Peripherals
VDD
+
P
VDD
From WDT
Reset Source
VSS
VDD
RST
1K
To Other
On-board
Circuitry