1. Operating ICC is measured with all outpu" />
參數(shù)資料
型號: AT89C51ED2-RDRUM
廠商: Atmel
文件頁數(shù): 19/137頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8051 64K 5V 64-VQFP
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 標準包裝
其它名稱: AT89C51ED2-RDRUMDKR
115
4235K–8051–05/08
AT89C51RD2/ED2
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 25-4), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 25-2).
3. Power-down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
VOH1
Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
VCC = 5V ± 10%
IOH = -200 A
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC
V
VCC = 2.7V to 5.5V
IOH = -10 A
RRST
RST Pull-down Resistor
50
200(5)
250
k
IIL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
A
VIN = 0.45V
ILI
Input Leakage Current
±
10
A
0.45V < VIN < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
A
VIN = 2.0V
C
IO
Capacitance of I/O Buffer
10
pF
FC = 3 MHz
T
A = 25°C
I
PD
Power-down Current
75
150
A
2.7 < V
CC < 5.5V
(3)
I
CCOP
Power Supply Current on normal mode
0.4 x Frequency (MHz) + 5
mA
V
CC = 5.5V
(1)
I
CCIDLE
Power Supply Current on idle mode
0.3 x Frequency (MHz) + 5
mA
V
CC = 5.5V
(2)
I
CCWRITE
Power Supply Current on flash or EEdata write
0.8 x Frequency (MHz) + 15
mA
V
CC = 5.5V
t
WRITE
Flash or EEdata programming time
7
17
ms
2.7 < V
CC < 5.5V
VPFDP
Internal POR/PFD VPFDP threshold
2.25
2.5
2.69
V
VPFDM
Internal POR/PFD VPFDM threshold
2.15
2.35
2.62
V
Vhyst
Internal POR/PFD Hysteresys
70
140
250
mV
Vcc
dV/dt
Maximum Vcc Power supply slew rate(7)
0.1
V/s
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
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