參數(shù)資料
型號(hào): AT89C51AC3-RLTIM
廠商: Atmel
文件頁數(shù): 121/140頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K 44VQFP
標(biāo)準(zhǔn)包裝: 160
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
2009 Microchip Technology Inc.
DS70286C-page 79
dsPIC33FJXXXGPX06/X08/X10
TABLE 6-1:
RESET FLAG BIT OPERATION
6.1
Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
further details.
TABLE 6-2:
OSCILLATOR SELECTION VS
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
6.2
Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Flag Bit
Setting Event
Clearing Event
TRAPR (RCON<15>)
Trap conflict event
POR, BOR
IOPUWR (RCON<14>)
Illegal opcode or uninitialized
W register access
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET
instruction
POR, BOR
WDTO (RCON<4>)
WDT time-out
PWRSAV
instruction, POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP
instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE
instruction
POR, BOR
BOR (RCON<1>)
BOR, POR
POR (RCON<0>)
POR
Note: All Reset flag bits may be set or cleared by the user software.
Reset Type
Clock Source Determinant
POR
Oscillator Configuration bits
(FNOSC<2:0>)
BOR
MCLR
COSC Control bits
(OSCCON<14:12>)
WDTR
SWR
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