參數(shù)資料
型號(hào): AT89C5130A-PUTUM
廠商: Atmel
文件頁(yè)數(shù): 20/188頁(yè)
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K USB 32QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 1,300
系列: AT89C513x
核心處理器: C52X2
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
其它名稱: AT89C5130A-PUTIM
AT89C5130A-PUTIM-ND
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dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 116
2007-2011 Microchip Technology Inc.
10.2
Open-Drain Configuration
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired 5V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See “Pin Diagramsfor the available pins and their
functionality.
10.3
Configuring Analog Port Pins
The AD1PCFG and TRIS registers control the
operation of the analog-to-digital (A/D) port pins. The
port pins that are desired as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (VOH or VOL)
will be converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
10.4
I/O Port Write/Read Timing
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP. Examples are shown in Example 10-1
and Example 10-2. This also applies to PORT bit oper-
ations, such as BSET PORTB, # RB0, which are single
cycle read-modify-write. All PORT bit operations, such
as MOV PORTB, W0 or BSET PORTB, # RBx, read
the pin and not the latch.
10.5
Input Change Notification
The input change notification function of the I/O ports
allows
the
dsPIC33FJ32GP202/204
and
dsPIC33FJ16GP304 devices to generate interrupt
requests to the processor in response to a
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 31 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Four control registers are associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
EXAMPLE 10-1:
PORT WRITE/READ
EXAMPLE 10-2:
PORT BIT OPERATIONS
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
MOV
0xFF00, W0
;Configure PORTB<15:8> as inputs
MOV
W0, TRISBB
;and PORTB<7:0> as outputs
NOP
;Delay 1 cycle
BTSS
PORTB, #13
;Next Instruction
Incorrect:
BSET
PORTB, #RB1
;Set PORTB<RB1> high
BSET
PORTB, #RB6
;Set PORTB<RB6> high
Correct:
BSET
PORTB, #RB1
;Set PORTB<RB1> high
NOP
BSET
PORTB, #RB6
;Set PORTB<RB6> high
NOP
Preferred:
BSET
LATB, LATB1
;Set PORTB<RB1> high
BSET
LATB, LATB6
;Set PORTB<RB6> high
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