參數(shù)資料
型號(hào): AT89C51-24PI
廠商: Atmel
文件頁(yè)數(shù): 13/17頁(yè)
文件大?。?/td> 0K
描述: IC MICRO CTRL 24MHZ 40DIP
標(biāo)準(zhǔn)包裝: 9
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: UART/USART
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
AT89C51
5
Figure 2. External Clock Drive Configuration
Power-down Mode
In the power-down mode, the oscillator is stopped, and the
instruction that invokes power-down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power-down mode is
terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before V
CC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the
additional features listed in the table below.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
essary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
Lock Bit Protection Modes
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
No program lock features
2
P
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further programming of the Flash is disabled
3
P
U
Same as mode 2, also verify is disabled
4
P
Same as mode 3, also external execution is disabled
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