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參數(shù)資料
| 型號： | AT87F51-24JI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MICRO CTRL 24MHZ 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | 87F |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 24MHz |
| 連通性： | UART/USART |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | OTP 快速閃存 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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When the AT87F51 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
This pin also receives the 12-volt programming enable volt-
age (VPP) during QuickFlash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Figure 1. Oscillator Connections
Note:
C1, C2 = 30 pF
± 10 pF for Crystals
= 40 pF
± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
C2
XTAL2
GND
XTAL1
C1
Status of External Pins During Idle and Power Down Modes
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
Data
Idle
External
1
Float
Data
Address
Data
Power Down
Internal
0
Data
Power Down
External
0
Float
Data
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