參數(shù)資料
型號(hào)： AT49BP1604T
廠商： ATMEL CORP
元件分類： DRAM
英文描述： 16-megabit Burst Mode 3-volt Only Flash Memory(16M位脈沖串模式3V閃速存儲(chǔ)器)
中文描述： 1M X 16 FLASH 3V PROM, 100 ns, PBGA40
封裝： BGA-40
文件頁(yè)數(shù)： 3/19頁(yè)
文件大小： 263K
代理商： AT49BP1604T
AT49BP1604(T)
3
used in the command sequences are not affected by enter-
ing the command sequences.
RESET:
A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET pin halts the present device operation and puts the
outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device
returns to Read or Standby mode, depending upon the
state of the control pins. By applying a 12 ± 0.5V input sig-
nal on the RESET pin any sector can be reprogrammed
even if the sector lockout feature has been enabled.
ERASE:
Before a word can be reprogrammed it must be
erased. The erased state of the memory bits is a logical “1”.
The entire memory can be erased by using the Chip Erase
command or individual sectors can be erased by using the
Sector Erase commands.
CHIP ERASE:
Chip Erase is a six bus cycle operation. The
automatic Erase begins on the rising edge of the last WE
pulse. Chip Erase does not alter the data of the protected
sectors. After the full chip Erase the device will return back
to the read mode. The hardware reset during Chip Erase
will stop the Erase but the data will be of unknown state.
Any command during chip Erase except erase suspend will
be ignored.
SECTOR ERASE:
As an alternative to a full chip erase, the
device is organized into 40 sectors that can be individually
erased. The Sector Erase command is a six bus cycle
operation. The sector whose address is valid at the sixth
falling edge of WE will be erased provided the given sector
has not been protected.
WORD PROGRAMMING:
The device is programmed on a
word by word basis. Programming is accomplished via the
internal device command register and is a four bus cycle
operation. The programming address and data are latched
in the fourth cycle. The device will automatically generate
the required internal programming pulses. Please note that
a “0” cannot be programmed back to a “1”; only Erase oper-
ations can convert “0”s to “1”s. During the programming
mode, the clock signal must be held low or high and cannot
toggle.
SECTOR PROGRAMMING LOCKOUT:
Each sector has a
programming lockout feature. This feature prevents pro-
gramming of data in the designated sectors once the fea-
ture has been enabled. The sectors that are locked out can
contain secure code that can bring up the system. Enabling
the lockout feature will allow the boot code to stay in the
device while data in the rest of the memory is updated. This
feature does not have to be activated; any sector’s usage
as a write protected region is optional to the user. Once the
feature is enabled, the data in the protected sector can no
longer be erased or programmed when input levels of 5.5V
or less are used. Data in the remaining sectors can still be
changed through the regular programming method. To acti-
vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
SECTOR LOCKOUT DETECTION:
A software method is
available to determine if programming of a sector is locked
out. When the device is in the software product identifica-
tion mode (see Software product Identification Entry and
Exit sections) a read from address location 00002H within a
sector will show if programming the sector is locked out. If
the data on D0 is low, the sector can be programmed; if the
data on D0 is high, the program lockout feature has been
enabled and the sector cannot be programmed. The soft-
ware product identification exit code should be used to
return to standard operation.
SECTOR PROGRAMMING LOCKOUT OVERRIDE:
The
user can override the sector programming lockout by taking
the RESET pin to 12V ± 0.5 volts. By doing this protected
data can be altered through a chip erase, sector erase or
word programming. When the RESET pin is brought back
to TTL levels, the sector programming lockout feature is
again active.
POWER SAVE:
The power savings pin, PS, has an open
drain configuration which is actively pulled low during the
read operation. During non-read operations, the power sav-
ing pin can be driven high or low by the bus controller.
DATA POLLING:
The AT49BP1604(T) features DATA bar
polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last word loaded will
result in the complement of the loaded data on D7. Once
the program or erase cycle has been completed, true data
will be read from the device. Data bar polling may begin at
any time during the program cycle. Please see “Status Bit
Table” on page 18 for more details.
TOGGLE BIT:
In addition to DATA bar polling the
AT49BP1604(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in D6 toggling between a “1” and “0”.
Once the program cycle has completed, D6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
An additional toggle bit is available on D2 which can be
used in conjunction with the toggle bit which is available on
D6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the
D2 bit toggling. Please see “Status Bit Table” on page 18
for more details.
ERASE SUSPEND/RESUME:
The Erase suspend allows
the user to interrupt a Sector Erase operation and then per-
form a data read on the remaining sectors. This feature is
only allowed during the sector erase operation. The device
will take up to a maximum of 20 μs to suspend the Erase.
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