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參數(shù)資料
| 型號： | AT49BN1604T |
| 廠商： | Atmel Corp. |
| 英文描述： | 16-megabit Burst Mode 3-volt Only Flash Memory(16M位 3V猝發(fā)模式閃速存儲器) |
| 中文描述： | 16兆位突發(fā)模式3伏，只有閃存（1,600位3V的猝發(fā)模式閃速存儲器） |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 264K |
| 代理商： | AT49BN1604T |
AT49BN1604(T)
2
in-system programming. The output voltage can be sepa-
rately controlled down to 1.65V through the VCCQ supply
pin.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors. The end of program or Erase is detected by data
polling, or toggle bit.
A V
PP
pin is provided to improve program/erase times. This
pin does not need to be utilized. If it is not used the pin
should be connected to ground. To take advantage of
faster programming, the pin should supply 4.5 to 5.5 volts
during program and erase operations.
With V
PP
at 5V, a six byte command to remove the require-
ment of entering the three byte program sequence is
offered to further improve programming time. After entering
the six byte code, only single pulses on the write control
lines are required for writing into the device. This mode is
exited by powering down the device, by taking the RESET
pin to GND
or by a high to low transition on the V
PP
input.
This mode is not exited by the read reset command. Erase,
Erase Suspend/Resume and Read Reset commands will
not work while in this mode; if entered they will result in
data being programmed into the device. It is not recom-
mended that the six byte code reside in the software of the
final product but only exist in external programming code.
Device Operation
RANDOM READ:
The random read operation of the device
is controlled by CE, OE, and AVD inputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention. The data at the address location
defined by A0-A19 and captured by the AVD signal will be
read when CE and OE are low. The address location
passes into the device when CE and AVD are low; the
address is latched on the low to high transition of AVD. Low
input levels on the OE and CE pins allow the data to be
driven out of the device. The access time is measured from
stable address, falling edge of AVD or falling edge of CE,
whichever occurs last. The BAA signal must be held high,
and no clock signal is provided during random reads.
BURST READ:
The burst read operation of the device is
controlled by CE, OE, CLK, BAA and AVD inputs. The initial
read location is determined as for the random read opera-
tion; it can be any memory location in the device. A low
input on the BAA signal indicates that a burst read will
occur. In the burst access, the address is latched on the ris-
ing edge of the first clock pulse when AVD is low or the ris-
TSOP
Top View
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VCCQ
RDY
NC
A16
A15
A14
A13
A12
A11
GND
AVD
CLK
DC
VCC
WE
RESET
VPP
A19
A18
A17
A10
A9
A8
A7
A6
CE
BAA
GND
NC
GND
I/O15
I/O7
I/O14
I/O6
GND
I/O13
I/O5
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
VCCQ
I/O9
I/O1
I/O8
I/O0
A5
A4
A3
A2
A1
A0
OE
NC
BGA
Top View
A
B
C
D
E
F
1
2
3
4
5
6
7
8
9
10
NC
VSS
BAA
A1
A0
OE
CE
A6
A7
A4
A3
A2
A8
A9
A10
I/O8
I/O0
A5
A17
A18
A19
NC
I/O9
I/O1
VPP
RESET
NC
NC
I/O2
VCCQ
VCC
WE
DC
NC
I/O10
I/O3
AVD
CLK
VSS
I/O11
I/O4
I/O12
A12
A11
A13
I/O5
I/O13
VSS
A15
A14
A16
NC
I/O6
I/O14
VCCQ
RDY
NC
I/O7
I/O15
VSS
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