參數(shù)資料
型號： AT32UC3L032-AUR
廠商： Atmel
文件頁數(shù)： 94/174頁
文件大小： 0K
描述： IC MCU AVR32 32K FLASH 48TQFP
產(chǎn)品培訓(xùn)模塊： AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝： 1
系列： AVR®32 UC3 L
核心處理器： AVR
芯體尺寸： 32-位
速度： 50MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 剪切帶 (CT)
配用： ATSTK600-RC34-ND - STK600 ROUTING CARD AVR
其它名稱： AT32UC3L032-AURCT
45
32099I–01/2012
AT32UC3L016/32/64
7.5.10
Priority
If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel zero the highest priority.
7.5.11
Error Handling
If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error
will occur when the PDCA tries to perform a transfer. When an error occurs, the Transfer Error
bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the
error will be stopped. In order to restart the channel, the user must program the Memory
Address Register to a valid address and then write a one to the Error Clear bit in the Control
Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be gener-
ated when a transfer error occurs.
7.5.12
Peripheral Event Trigger
Peripheral events can be used to trigger PDCA channel transfers. Peripheral Event synchroniza-
tions are enabled by writing a one to the Event Trigger bit in the Mode Register (MR.ETRIG).
When set, all DMA requests will be blocked until a peripheral event is received. For each periph-
eral event received, only one data item is transferred. If no DMA requests are pending when a
peripheral event is received, the PDCA will start a transfer as soon as a peripheral event is
detected. If multiple events are received while the PDCA channel is busy transferring data, an
overflow condition will be signaled in the Peripheral Event System. Refer to the Peripheral Event
System chapter for more information.
7.6
Performance Monitors
Up to two performance monitors allow the user to measure the activity and stall cycles for PDCA
transfers. To monitor a PDCA channel, the corresponding channel number must be written to
one of the MON0/1CH fields in the Performance Control Register (PCONTROL) and a one must
be written to the corresponding CH0/1EN bit in the same register.
Due to performance monitor hardware resource sharing, the two monitor channels should NOT
be programmed to monitor the same PDCA channel. This may result in UNDEFINED perfor-
mance monitor behavior.
7.6.1
Measuring mechanisms
Three different parameters can be measured by each channel:
The number of data transfer cycles since last channel reset, both for read and write
The number of stall cycles since last channel reset, both for read and write
The maximum latency since last channel reset, both for read and write
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load, and maximum bus latency.
Each of the counters has a fixed width, and may therefore overflow. When an overflow is
encountered in either the Performance Channel Data Read/Write Cycle registers (PRDATA0/1
and PWDATA0/1) or the Performance Channel Read/Write Stall Cycles registers (PRSTALL0/1
and PWSTALL0/1) of a channel, all registers in the channel are reset. This behavior is altered if
the Channel Overflow Freeze bit is one in the Performance Control register (PCON-
TROL.CH0/1OVF). If this bit is one, the channel registers are frozen when either DATA or
STALL reaches its maximum value. This simplifies one-shot readout of the counter values.
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