參數(shù)資料
型號: AT32UC3C2512C-Z2ZR
廠商: Atmel
文件頁數(shù): 85/109頁
文件大?。?/td> 0K
描述: IC MCU AVR32 512K FLASH 64QFN
產品培訓模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 C
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: CAN,以太網,I²C,IrDA,LIN,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 11x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 標準包裝
其它名稱: AT32UC3C2512C-Z2ZRDKR
77
9166DS–AVR-01/12
AT32UC3C
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
Where
is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA.
is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
Where
is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA.
is the
SPI master setup time. Please refer to the SPI masterdatasheet for
.
is the maxi-
mum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
7.9.5
TWIM/TWIS Timing
Figure 7-50 shows the TWI-bus timing requirements and the compliance of the device with
them. Some of these requirements (tr and tf) are met by the device without requiring user inter-
vention. Compliance with the other requirements (tHD-STA, tSU-STA, tSU-STO, tHD-DAT, tSU-DAT-I2C, tLOW-
I2C, tHIGH, and fTWCK) requires user intervention through appropriate programming of the relevant
Table 7-49.
SPI Timing, Slave Mode(1)
Symbol
Parameter
Conditions
Min
Max
Units
SPI6
SPCK falling to MISO delay
external
capacitor =
40pF
31
ns
SPI7
MOSI setup time before SPCK rises
0
ns
SPI8
MOSI hold time after SPCK rises
7
ns
SPI9
SPCK rising to MISO delay
32
ns
SPI10
MOSI setup time before SPCK falls
1.5
ns
SPI11
MOSI hold time after SPCK falls
5
ns
SPI12
NPCS setup time before SPCK rises
4
ns
SPI13
NPCS hold time after SPCK falls
2.5
ns
SPI14
NPCS setup time before SPCK falls
3.5
ns
SPI15
NPCS hold time after SPCK rises
2.5
ns
fSPCKMAX
MIN fCLKSPI
1
SPIn
------------
(,
)
=
SPIn
fCLKSPI
fSPCKMAX
MIN fPINMAX
1
SPIn tSETUP
+
------------------------------------
(,
)
=
SPIn
tSETUP
tSETUP fPINMAX
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