參數(shù)資料
型號: AT32UC3A1128-AUT
廠商: Atmel
文件頁數(shù): 81/97頁
文件大?。?/td> 0K
描述: IC MCU AVR32 128KB FLASH 100TQFP
產(chǎn)品培訓(xùn)模塊: AVR UC3 Audio Application
MCU Product Line Introduction
AVR EVK1105 Digital Audio Gateway Kit
AVR® UC3 Introduction
標(biāo)準(zhǔn)包裝: 450
系列: AVR®32 UC3 A1
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: 以太網(wǎng),I²C,SPI,SSC,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 69
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
配用: ATSTK600-RC28-ND - STK600 ROUTING CARD AVR
ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATSTK600-TQFP100-ND - STK600 SOCKET/ADAPTER 100-TQFP
ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
82
AT32UC3A
(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to
an exception or to other errors derived from this corrupted read access.
Fix/Workaround
Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or
through the EBI. After these commands, read twice one flash page initialized to 00h in each
half part of the flash.
15.4.6
PDCA
1.
Wrong PDCA behavior when using two PDCA channels with the same PID.
Workaround/fix
The same PID should not be assigned to more than one channel.
15.4.7
TWI
1.
The TWI RXRDY flag in SR register is not reset when a software reset is performed.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
15.4.8
SDRAMC
1.
Code execution from external SDRAM does not work
Code execution from SDRAM does not work.
Fix/Workaround
Do not run code from SDRAM.
15.4.9
GPIO
1.
Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant
Only 11 GPIOs remain 5V tolerant (VIHmax=5V):PB01, PB02, PB03, PB10, PB19, PB20,
PB21, PB22, PB23, PB27, PB28.
Workaround/fix
None.
15.4.10
USART
1.
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None.
15.4.11
Processor and Architecture
1.
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
2.
RETE instruction does not clear SREG[L] from interrupts.
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning from interrupts with RETE.
3.
Exceptions when system stack is protected by MPU
32058KS–AVR32–01/12
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