參數(shù)資料
型號(hào)： ARD00354
廠商： Microchip Technology
文件頁(yè)數(shù)： 20/50頁(yè)
文件大?。?/td> 0K
描述： BOARD REF DESIGN MCP6N11/MCP6V2X
標(biāo)準(zhǔn)包裝： 1
每 IC 通道數(shù)： 1 - 單
放大器類型： 儀表
輸出類型： 滿擺幅
電流 - 輸出 / 通道： 30mA
工作溫度： -40°C ~ 125°C
電流供應(yīng)（主 IC）： 800µA
板類型： 完全填充
已供物品： 板，線纜
已用 IC / 零件： MCP6N11，MCP6001，MCP6V26，MCP6V27，PIC18F2553
2011 Microchip Technology Inc.
DS25073A-page 27
MCP6N11
4.0
APPLICATIONS
The MCP6N11 instrumentation amplifier (INA) is
manufactured using Microchip’s state of the art CMOS
process. It is low cost, low power and high speed,
making it ideal for battery-powered applications.
4.1
Basic Performance
4.1.1
STANDARD CIRCUIT
Figure 4-1 shows the standard circuit configuration for
these INAs. When the inputs and output are in their
specified ranges, the output voltage is approximately:
EQUATION 4-1:
FIGURE 4-1:
Standard Circuit.
For normal operation, keep:
VIP, VIM, VREF and VFG between VIVL and VIVH
VIP – VIM (i.e., VDM) between VDML and VDMH
VOUT between VOL and VOH
4.1.2
ARCHITECTURE
Figure 4-2 shows the block diagram for these INAs.
FIGURE 4-2:
MCP6N11 Block Diagram.
The input offset voltage (VOS) is corrected by the
voltage VTR. Each time a VOS Calibration event occurs,
VTR is updated to the best value (at that moment).
These events are triggered by either powering up
(monitored by the POR) or by toggling the EN/CAL pin
high. The current out of GM3 (I3) is constant and very
small (assumed to be zero in the following discussion).
The input signal is applied to GM1. Equation 4-2 shows
the relationships between the input voltages (VIP and
VIM) and the common mode and differential voltages
(VCM and VDM).
EQUATION 4-2:
The negative feedback loop includes GM2, RM4, RF and
RG. These blocks set the DC open-loop gain (AOL) and
the nominal differential gain (GDM):
EQUATION 4-3:
AOL is very high, so I4 is very small and I1 + I2 ≈ 0. This
makes the differential inputs to GM1 and GM2 equal in
magnitude and opposite in polarity. Ideally, this gives:
EQUATION 4-4:
For an ideal part, changing VCM, VSS or VDD produces
no change in VOUT. VREF shifts VOUT as needed.
The different GMIN options change GM1, GM2 and the
internal compensation capacitor. This results in the
performance trade-offs shown in Table 1.
VOUT ≈ VREF +GDMVDM
Where:
GDM =1 +RF /RG
VOUT
VIP
VDD
VIM
VREF
VFG
RF
RG
U1
MCP6N11
RF
VFG
VOUT
Low Power
VSS
VDD
EN/CAL
VOUT
VOS Calibration
VREF
RM4
GM2
Σ
I2
VREF
I4
GM3
I3
VTR
RG
VIP
VIM
GM1
I1
VIP
VIM
POR
V
IP
V
CM
V
DM 2
+
=
V
IM
V
CM
V
DM 2
–
=
V
CM
V
IP
V
IM
+
() 2
=
V
DM
V
IP
V
IM
–
=
A
OL
G
M2RM4
=
G
DM
1R
F RG
+
=
V
FG
V
REF
–
()
V
DM
=
V
OUT
V
DMGDM
V
REF
+
=
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