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參數(shù)資料
| 型號： | AR-20441-11 |
| 廠商： | Conexant Systems, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:15; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:28; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:28-17 RoHS Compliant: No |
| 中文描述： | AccessRunner ADSL調(diào)制解調(diào)器的PCI設備的應用設置 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 159K |
| 代理商： | AR-20441-11 |
Controller-less ADSL Modem Device Set for PCI Applications
AccessRunner
Doc. No. 100394B
October 19, 1999
Conexant
Proprietary Information
11
Table 4. 11627 Pin Signals by Group
Pin Name
I/O
Description
AFE ANALOG-to-DIGITAL INTERFACE
RX[15:0]
I
Receive Data Lines
In the parallel mode of operation, data is clocked by the signal ADC_CLK using the full
data bus. In the serial mode of operation, a strobe signal (AFE_STR#) from the AFE
shall trigger the transfer of data over a programmable width serial bus.
ADC_CLK
O
Receive Clock for Parallel Mode
CLIP#
O
Clip Interrupt
This signal is used for monitoring incoming data for saturation. Goes low for one clock
(ADC_CLK) cycle whenever clipping is detected.
AFE DIGITAL-to-ANALOG INTERFACE
TX[15:0]
O
Transmit Data Lines
In the parallel mode of operation, data is clocked by the signal DAC_CLK using the full
data bus. In the serial mode of operation, a strobe signal (AFE_STR#) from the AFE
shall trigger the transfer of data over a programmable width serial bus.
DAC_CLK
O
Transmit Clock for Parallel Mode
FILTER_CLK
O
AFE Filter Clock
This signal is used by the DAC interface block to strobe the external AFE filters.
AFE_STR#
I
AFE Strobe Signal
DIGITAL INTERFACE (DI)
TLXCK_EN
I
LSX Transmit Data Clock Generation Enable
T_CLK_LS0
I/O
Transmit Data Clock (LS0)
T_CLK_LS1
I/O
Transmit Data Clock (LS1)
T_DAT_LS0
I
Transmit Data (LS0)
T_DAT_LS1
I
Transmit Data (LS1)
R_CLK_LS0
I
Receive Data Clock (LS0)
R_CLK_LS1
I
Receive Data Clock (LS1)
R_DAT_LS0
O
Receive Data (LS0)
R_DAT_LS1
O
Receive Data (LS1)
R_CLK_AS0
I
Receive Data Clock (AS0)
R_CLK_AS1
I
Receive Data Clock (AS1)
R_DAT_AS0
O
Receive Data (AS0)
R_DAT_AS1
O
Receive Data (AS1)
R_NCO_LS0
O
Receive LS0 NCO Output
R_NCO_LS1
O
Receive LS1 NCO Output
R_NCO_AS0
O
Receive AS0 NCO Output
R_NCO_AS1
O
Receive AS1 NCO Output
BIT_CLOCK
O
Serial Data Bit Clock Output
Used to synchronize the serial input and output data bit streams, enables, and
superframe qualifiers.
T_FAST_BYTE#
O
Transmit Fast Data Bit Input Enable
T_INTER_BYTE#
O
Transmit Interleaved Data Bit Input Enable
R_FAST_FRAME#
O
Receive Fast Data Bit Output Frame Qualifier
R_FAST_SUPER#
O
Receive Fast Data Bit Output Superframe Qualifier
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