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參數(shù)資料
| 型號(hào)： | APV-FREQ-LC-T |
| 廠商： | ABRACON CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 38 MHz - 640 MHz, CMOS OUTPUT |
| 文件頁數(shù)： | 2/2頁 |
| 文件大小： | 750K |
| 代理商： | APV-FREQ-LC-T |
Dimensions: inch (mm)
MARKING:
- TUH
Frequency
T=First “ten” digit of frequency,
U=First “unit” of frequency,
H=First “tenth” digit of freq,
Ex: 100 for 10.0MHz;
143 for 14.31818 MHz)
- APV ZYX
(Z: Month, A to L;
Y: Year, 5 for 2005;
X: Traceability Code)
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
|||||||||||||||
APV SERIES
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
PIN ASSIGNMENTS:
OPTIONS AND PART IDENTIFICATION (Left blank if standard):
PECL & LVDS DRAWING:
Dimensions: inch (mm)
CMOS DRAWING:
Temperature:
E for -20°C to +70°C
L for -40°C to +85°C
APVX - Frequency - Temperature - Frequency Stability - Output - Packaging
Packaging option: T for Tape and Reel
(1,000pcs/reel)
PIN #
NAME
DESCRIPTION
1
2
3
4
5
6
Tri-state
NC
GND
Q
VDD
Tri-state
No Connect
Ground
PECL, LVDS
Complimentary PECL, LVDS
VDD Connection
TRI-STATE PIN OPERATION:
OUTPUT TYPE OPTION PIN 1 LOGIC LEVEL*
OUTPUT STATE
P
P1
V
C
PECL
PECL1
LVDS
CMOS
0 (Default)
1
0
1 (Default)
0
1 (Default)
Enabled
Tri-state
Enabled
Tri-state
Enabled
Tri-state
Enabled
*Connect to VDD from logic level "1", connect to ground for logic level "0".
Output options:
P = PECL
P1 = PECL1
V = LVDS
C = CMOS
Stability options:
R for ± 25 ppm max
S for ± 20 ppm max
PIN #
NAME
1
2
3
4
Tri-state
GND/Case
Output
Vdd
Vdd options:
Blank (3.3Vdc±10%V)
1 (2.5Vdc±10%V)
re
v3.1-8/06
: PRELIMINARY
5.0 x 7.0 x 1.8mm
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