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參數(shù)資料
| 型號： | APD-240G064 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Plasma Panel Display Modules |
| 中文描述： | 等離子顯示器模塊 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 150K |
| 代理商： | APD-240G064 |
Document Number: 37046
Revision 21-Dec-00
www.vishay.com
42
APD-240G064
Vishay Dale
PARALLEL INTERFACE
J2, PARALLEL DATA CONNECTOR.
Mates with 3M Tyco AMP 746285-6, 26 pin, IDC connector.
Note:
PAR should be jumper selected on jumper block W1 for
proper parallel interface operation.
*Note:
The maximum VDC draw denotes a power up condition
when the DC converter starts. Typical duration is 15-30 mS.
*Unit may be powered from + 5V to + 24V. Contact factory for
current draw at voltages other than + 12V and pin connection J2.
+ 12V
±
0.6V
2.5A Max.*, 1.25 A Typ
.
VDC
POWER SUPPLY:
(Recommended)
CONNECTOR
J1
PIN
1
2
3
4
SIGNAL
+ 12 V
GROUND
GROUND
Reserved
Mates to Tyco AMP *1-480424-0 housing (1 rqr.)
*350689-1 socket pins (4 rqr.)
POWER SUPPLY CONNECTION
Note:
Input load is one 74 HCT type input with 4.7k to V
cc
. Outputs
are 74 HC type.
Once data write is complete, BUSY signal is output. BUSY
signal = "1" during data disposition and while the
communication buffer is full.
DATA WRITE:
When WR changes from "0" to "1" while
US = "0" and RD = "1", data is latched.
DATA READ:
When RD = "0" while US = "0". WR = "1", and
DP = "1", data may be read by the host.
POWER UP CONDITION
Immediately upon power up the following is set:
The module is in the text mode.
The screen will have a message printed as follows:
RAM OK
mm-dd-yy
This message indicates the hardware test has passed
successfully. The "mm-dd-yy" indicates the date the firm-
ware was released.
ROM OK
INPUT/OUTPUT TIMING DIAGRAM, J2
LOGIC LEVEL:
L = 0.0 V minimum to 0.8 V maximum.
H = 2.2 V minimum to 5.0 V maximum..
X = Don't care.
DP
X
H
X
RD
H
L
X
WR
_|
ˉˉ
H
X
US
L
L
H
FUNCTION
Write character or control code.
Read data from display while low.
Input/Output inhibited.
BU
L
X
X
PARALLEL INTERFACE
PIN
1, 3, 5, 7, 9, 11, 13, 15
17
21
6, 8, 12, 14, 16, 18, 20, 22
23
19
25
4
24
2, 26
10
DESCRIPTION
Data written to and read from the display unit through an 8 bit
bi-directional data bus.
Write data on low to high transmit.
Read data while low.
Not connected.
Reset display to power-up condition when low, operate while high.
Read and Write commands only influence display while US is low.
Blank display while BL is low but maintain cursor and data.
Display at full brightness when high or half brightness when low.
When BUSY is high, no further data or commands should be given.
Common to both power supply input and host data interface.
Data is ready to be read when the DATA PRESENT signal is high.
FUNCTION
D0-D7 (Data Bus)
(input/output)
WRITE (WR)
(input)
READ (RD)
(input)
N/C
RESET
(input)
US (Unit Select)
(input)
BLANK (BL)
(input)
BRIGHT/DIM (input)
(BUSY (BU)
(output)
GROUND
DATA PRESENT
(DP) (output)
Power up RESET cycle on display module takes approxi-
mately
250 mS to complete. It is suggested the user wait for that
time period to elapse before entering data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APD240G0640001S51 | 功能描述:等離子體顯示器 240x64 Module RoHS:否 產(chǎn)品種類:Plasma Graphic Display Module 類型:Graphics Displays 制造商:Vishay/Dale |
| APD-240G120 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Plasma Panel Display Modules 240 x 120 Graphics Display with Drive Electronics and Controller |
| APD-240G120-5 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Plasma Panel Display Modules 240 x 120 Graphics Display with Drive Electronics and Controller |
| APD240G120A | 制造商:Vishay Dale 功能描述:APD-240G120A G01 制造商:Vishay Dale 功能描述:PLASMA GRAPHIC DISPLAY MODULE, 240X120, 12V; Resolution:240 x 120; Character Format:Dot Matrix; Viewing Area (H x W):95mm x 191.77mm; Supply Current:400mA; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Voltage:5.25V ;RoHS Compliant: No |
| APD240KDTR-G1 | 制造商:BCDSEMI 制造商全稱:BCD Semiconductor Manufacturing Limited 功能描述:SCHOTTKY BARRIER RECTIFIERS |
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