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Document Number: 37008
Revision 05-Dec-00
www.vishay.com
2
APD-128G064
Vishay Dale
Plasma Display Modules
128 x 64 Graphics Display with
Drive Electronics and TTL Level Data Interface
FEATURES
TTL level video interface
Slim profile
Bright and vivid graphics
Low DC power consumption
> 50,000 hour MTBF
30:1 contrast ratio
Very affordable
ELECTRICAL SPECIFICATIONS
Voltage (s) Required:
+ 75 VDC, - 110 VDC, + 5 VDC, Vcc
+ 12 VDC. (12 VDC to be referenced to - 110 VDC)
Power Required:
Typical = 2 watts. Maximum = 7 watts.
OPTICAL SPECIFICATIONS
Viewing Area:
5.108” [129.74mm] W x 2.548” [64.72mm] L.
Character Array:
16 x 8 (using 8 x 8 block), 21 x 8 (using 6
x 8 block).
Character Size:
0.267” [6.78mm] H x 0.187” [4.75mm] W.
Pixel Size:
0.028” [.711mm] square.
Pixel Pitch:
0.040” [1.016mm].
Luminance:
50 foot lamberts.
The APD-128G064 DC plasma display offers viewing qualities designers seek such as high contrast, viewing angle of 150
°
C
minimum and excellent readability. Its bright (50 foot Lambert minimum) with characters and graphics figures presented in a
pleasing neon orange color against a black background. Plasma is much more readable and eye-pleasing than liquid crystal or
vacuum fluorescent displays and is filterable to red, amber or neutral density.
These plasma display panels are driven in a standard row-column refresh method much like a CRT display. The designer need
only supply TTL level signals for SERIAL DATA, DOT CLOCK, COLUMN LATCH, ROW DATA, ROW CLOCK and DISPLAY
ENABLE. The SERIAL DATA is entered with the DOT CLOCK up to frequencies as high as 8mHz. After a row of 128 pixels is
clocked in, the COLUMN LATCH signal is toggled and the data is latched. At the time the data is latched, the display is breifly
disabled using the DISPLAY ENABLE signal, then the row pointer is advanced with the ROW CLOCK signal. Once each frame
the ROW DATA must be asserted to synchronize the column serial data with the beginning row. The recommended scanning
frequency is approximately 70 Hz, but may be as high as 200 Hz. The high clock rate on the data clock allows for rapid refresh
and maximum access time to the refresh jam.
STANDARD ELECTRICAL SPECIFICATIONS
DESCRIPTION
SYMBOL
MIN.
TYP.
MAX.
UNITS
Logic Supply
Vcc
+ 4.5
+ 5.0
+ 5.5
VDC
Anode Supply
Vsp
-
+ 75
+ 80
VDC
Cathode Supply
Vsn
-
- 110
- 125
VDC
Cathode Control**
Vrw
+ 10.8
+ 12.0
+ 15.0
VDC
Total + Vsp & - Vsn
Vtot
170
185
205
VDC
Logic 1 Input
Vih
2.0
-
-
VDC
Logic 0 Input
Vil
-
-
0.8
VDC