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鍨嬭櫉(h脿o)锛� APA750-PQG208I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 142/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 750K 208-PQFP
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绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 158
闁€鏁�(sh霉)锛� 750000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
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ProASICPLUS Flash Family FPGAs
2- 56
v5.9
Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-29 Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-53 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 0掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
鈫�
2.0
ns
OCH
Old DO valid from RCLKS
鈫�
0.75
ns
RACH
RADDR hold from RCLKS
鈫�
0.5
ns
RACS
RADDR setup to RCLKS
鈫�
1.0
ns
RDCH
RDB hold from RCLKS
鈫�
0.5
ns
RDCS
RDB setup to RCLKS
鈫�
1.0
ns
RPCA
New RPE access from RCLKS
鈫�
4.0
ns
RPCH
Old RPE valid from RCLKS
鈫�
1.0
ns
RCLKS
RPE
DO
New Valid Data Out
Cycle Start
New RPE Out
RADDR
New Valid
Address
RDB, RBLKB
tRACS
tOCA
tRPCH
tOCH
tRPCA
tCML
tCMH
tCCYC
tRACH
tRDCH
tRDCS
Old Data Out
Old RPE Out
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