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鍨嬭櫉(h脿o)锛� APA750-PQ208I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 79/178闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 750K 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 158
闁€鏁�(sh霉)锛� 750000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-7
Power-Up Sequencing
While ProASICPLUS devices are live at power-up, the order
of VDD and VDDP power-up is important during system
start-up. VDD should be powered up simultaneously with
VDDP on ProASIC
PLUS devices. Failure to follow these
guidelines may result in undesirable pin behavior during
system start-up. For more information, refer to Actel鈥檚
note.
LVPECL Input Pads
In addition to standard I/O pads and power pads,
ProASICPLUS devices have a single LVPECL input pad on
both the east and west sides of the device, along with
AVDD and AGND pins to power the PLL block. The
LVPECL pad cell consists of an input buffer (containing a
low voltage differential amplifier) and a signal and its
complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).
The LVPECL input pad cell differs from the standard I/O
cell in that it is operated from VDD only.
Since it is exclusively an input, it requires no output
signal, output enable signal, or output configuration
bits. As a special high-speed differential input, it also
does not require pull-ups. Recommended termination
for LVPECL inputs is shown in Figure 2-7. The LVPECL pad
cell compares voltages on the PPECL (I/P) pad (as
illustrated in Figure 2-8) and the NPECL pad and sends
the results to the global MUX (Figure 2-11 on page 2-11).
This high-speed, low-skew output essentially controls the
clock conditioning circuit.
LVPECLs are designed to meet LVPECL JEDEC receiver
standard levels (Table 2-5).
Figure 2-7 Recommended Termination for LVPECL Inputs
Figure 2-8 LVPECL High and Low Threshold Values
Table 2-5
LVPECL Receiver Specifications
Symbol
Parameter
Minimum
Maximum
Units
VIH
Input High Voltage
1.49
2.72
V
VIL
Input Low Voltage
0.86
2.125
V
VID
Differential Input Voltage
0.3
VDD
V
+
_
PPECL
NPECL
From LVPECL Driver
Data
Z = 50
0
Z = 50
0
R = 100
2.72
2.125
1.49
0.86
Voltage
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