ProASICPLUS Flash Family FPGAs v5.9 2-17 Logic Tile Timing Characteristics
參數(shù)資料
型號： APA750-FG896A
廠商： Microsemi SoC
文件頁數(shù)： 99/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 750K 896-FBGA
標準包裝： 27
系列： ProASICPLUS
RAM 位總計： 147456
輸入/輸出數(shù)： 562
門數(shù)： 750000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 896-BGA
供應(yīng)商設(shè)備封裝： 896-FBGA（31x31）
ProASICPLUS Flash Family FPGAs
v5.9
2-17
Logic Tile Timing Characteristics
Timing characteristics for ProASICPLUS devices fall into
three categories: family dependent, device dependent,
and design dependent. The input and output buffer
characteristics are common to all ProASICPLUS family
members. Internal routing delays are device dependent.
Design dependency means that actual delays are not
determined until after placement and routing of the
user’s design are complete. Delay values may then be
determined by using the Timer utility or by performing
simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
timing-critical paths. Critical nets are determined by net
property assignment prior to place-and-route. Refer to
the Actel Designer User’s Guide or online help for details
on using constraints.
Timing Derating
Since ProASICPLUS devices are manufactured with a
CMOS process, device performance will vary with
temperature, voltage, and process. Minimum timing
parameters
reflect
maximum
operating
voltage,
minimum operating temperature, and optimal process
variations. Maximum timing parameters reflect minimum
operating voltage, maximum operating temperature,
and
worst-case
process
variations
(within
process
specifications). The derating factors shown in Table 2-9
should be applied to all timing data contained within
this datasheet.
All timing numbers listed in this datasheet represent
sample timing characteristics of ProASICPLUS devices.
Actual timing delay values are design-specific and can be
derived from the Timer tool in Actel’s Designer software
after place-and-route.
Table 2-9
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VDD = 2.3 V)
–55°C
–40°C
0°C
25°C
70°C
85°C
110°C
125°C
135°C
150°C
2.3 V
0.84
0.860.910.941.001.021.05
1.13
1.181.27
2.5 V
0.81
0.820.870.900.950.981.01
1.09
1.131.21
2.7 V
0.77
0.790.830.860.910.930.96
1.04
1.081.16
Notes:
1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 175°C.
2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.
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