ProASICPLUS Flash Family FPGAs v5.9 2-9 The TAP controller receives two control " />
參數(shù)資料
型號： APA300-PQ208A
廠商： Microsemi SoC
文件頁數(shù)： 90/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 300K 208-PQFP
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 73728
輸入/輸出數(shù)： 158
門數(shù)： 300000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
v5.9
2-9
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
ProASICPLUS devices support three types of test data
registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other
register needs to be accessed in a device. This speeds up
test data transfer to other devices in a test data path.
The 32-bit device identification register is a shift register
with four fields (lowest significant byte (LSB), ID number,
part number and version). The boundary-scan register
observes and controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output, and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Figure 2-10 TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
Select-DR-
Scan
Capture-DR
Shift-DR
Exit-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-
Scan
Capture-IR
Shift-IR
Exit-IR
Pause-IR
Exit2-IR
Update-IR
1
0
1
0
00
1
00
1
0
1
0
相關(guān)PDF資料
PDF描述
A54SX32A-BGG329I IC FPGA SX 48K GATES 329-BGA
A54SX32A-1BG329 IC FPGA SX 48K GATES 329-BGA
A54SX32A-BG329I IC FPGA SX 48K GATES 329-BGA
A54SX32A-1BGG329 IC FPGA SX 48K GATES 329-BGA
A54SX72A-FFG256 IC FPGA SX-A 108K 256-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA300-PQ208I 功能描述:IC FPGA PROASIC+ 300K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
APA300-PQ208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 300K Gates 180MHz 0.22um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays
APA300-PQ208MX319 制造商:Microsemi Corporation 功能描述:PROASICPLUS? 300K GATES 5MHZ MILITARY FLASH 2.5V 208 QFP - Trays
APA300-PQ896A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs
APA300-PQB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*