ProASICPLUS Flash Family FPGAs 2- 6 v5.9 Input/Output Blocks To" />
參數(shù)資料
型號： APA1000-CGS624B
廠商： Microsemi SoC
文件頁數(shù)： 68/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 1M 624-CGA
標準包裝： 1
系列： ProASICPLUS
RAM 位總計： 202752
輸入/輸出數(shù)： 440
門數(shù)： 1000000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 通孔
封裝/外殼： 624-BCCGA
供應(yīng)商設(shè)備封裝： 624-CCGA（32.5x32.5）
ProASICPLUS Flash Family FPGAs
2- 6
v5.9
Input/Output Blocks
To meet complex system demands, the ProASICPLUS
family offers devices with a large number of user I/O
pins; up to 712 on the APA1000. Table 2-3 shows the
available supply voltage configurations (the PLL block
uses an independent 2.5 V supply on the AVDD and
AGND pins). All I/Os include ESD protection circuits. Each
I/O has been tested to 2000 V to the human body model
(per JESD22 (HBM)).
Six or seven standard I/O pads are grouped with a GND
pad and either a VDD (core power) or VDDP (I/O power)
pad. Two reference bias signals circle the chip. One
protects the cascaded output drivers, while the other
creates a virtual VDD supply for the I/O ring.
I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a tristate driver, or a bidirectional
buffer (Figure 2-6 and Table 2-4).
Table 2-3
ProASICPLUS I/O Power Supply Voltages
VDDP
2.5 V
3.3 V
Input Compatibility
2.5V
3.3V
Output Drive
2.5V
3.3V
Figure 2-6 I/O Block Schematic Representation
3.3 V / 2.5 V
Signal Control
Pull-up
Control
Pad
Y
EN
A
3.3 V / 2.5 V Signal Control Drive
Strength and Slew-Rate Control
Table 2-4
I/O Features
Function
Description
I/O pads configured as inputs
Selectable 2.5 V or 3.3 V threshold levels
Optional pull-up resistor
Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be
configured as an input only, not a bidirectional buffer. This input type may be slower than
a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros
with an "S" in the standard I/O library have added Schmitt capabilities.
3.3 V PCI Compliant (except Schmitt trigger inputs)
I/O pads configured as outputs
Selectable 2.5 V or 3.3 V compliant output signals
2.5 V – JEDEC JESD 8-5
3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
3.3 V PCI compliant
Ability to drive LVTTL and LVCMOS levels
Selectable drive strengths
Selectable slew rates
Tristate
I/O pads configured as bidirectional
buffers
Selectable 2.5 V or 3.3 V compliant output signals
2.5 V – JEDEC JESD 8-5
3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
3.3 V PCI compliant
Optional pull-up resistor
Selectable drive strengths
Selectable slew rates
Tristate
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA1000-CGS624M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 624-Pin CCGA 制造商:Microsemi Corporation 功能描述:APA1000-CGS624M - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 1M 624CCGA
APA1000-CQ208B 功能描述:IC FPGA PROASIC+ 1M 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
APA1000-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 208-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 208CQFP - Trays
APA1000-CQ352B 功能描述:IC FPGA PROASIC+ 1M 352-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
APA1000-CQ352M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 352-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 352CQFP - Trays
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