ProASICPLUS Flash Family FPGAs 2- 40 v5.9 Table 2-25 DC" />
參數(shù)資料
型號: APA075-TQG144I
廠商: Microsemi SoC
文件頁數(shù): 125/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 75K 144-TQFP
標準包裝: 60
系列: ProASICPLUS
RAM 位總計: 27648
輸入/輸出數(shù): 107
門數(shù): 75000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
ProASICPLUS Flash Family FPGAs
2- 40
v5.9
Table 2-25 DC Specifications (3.3 V PCI Operation)1
Symbol
Parameter
Condition
Commercial/
Industrial2
Military/MIL-STD- 8832
Units
Min.
Max.
Min.
Max.
VDD
Supply Voltage for Core
2.3
2.7
2.3
2.7
V
VDDP
Supply Voltage for I/O Ring
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5VDDP VDDP + 0.5
0.5VDDP
VDDP + 0.5
V
VIL
Input Low Voltage
–0.5
0.3VDDP
–0.5
0.3VDDP
V
IIPU
Input Pull-up Voltage3
0.7VDDP
V
IIL
Input Leakage Current4
0 < VIN < VDDP
Std.
–10
10
–50
50
μA
VOH
Output High Voltage
IOUT = –500 A
0.9VDDP
V
VOL
Output Low Voltage
IOUT = 1500 A
0.1VDDP
V
CIN
Input Pin Capacitance (except CLK)
10
pF
CCLK
CLK Pin Capacitance
5
12
5
12
pF
Notes:
1. For PCI operation, use GL33, OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.
2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military.
3. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum
current at this input voltage.
4. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
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