- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375330 > AND8020 (Analog Devices, Inc.) Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure PDF資料下載
參數(shù)資料
| 型號(hào)： | AND8020 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結(jié)構(gòu) |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
AND8020/D
http://onsemi.com
15
SECTION 6. CAPACITIVE COUPLING
R
R
R
R
R
V
CC
V
BB
Although not strictly a termination, AC or capacitive
coupling is often used to provide features in conjunction
with proper termination. Such capabilities as hot swapping
capability, DC isolation to a receiver, and level shifting are
possible with capacitive coupling.
Data stream characteristics may impose restriction on
both termination and capacitive coupling. AC coupled
signals have the line DC blocked and will require a DC
restoration voltage, V
BIAS
, for the receiver input. Data in
unencoded NonReturntoZero (NRZ) format will require
DC restoration prior to AC coupling into a ECL receiver
input.
A sinusoidal waveform clock signal may be cap coupled
for conversion to a square wave with 50% duty cycle and
sharp rise and fall edges.
The capacitor used to couple the signal must have a
impedance rating of < 50 over the frequency range of the
input signal. Because large capacitors appear somewhat
inductive at high frequencies, it may be necessary to use a
small capacitor in parallel with a larger one to achieve
satisfactory operation.
A coupling capacitor and the signal load impedance form
an RC network which will boundary the duration of a pulse.
Values for the R (load and leakage total resistance) and C
(coupling capacitor) should be selected to provide a time
constant, T
C
, of at least 10x the pulse width. Data streams
may require larger T
C
values to retain logic levels.
Hot Swapping
The desire often arises to remove or install a receiver or
daughter card without powering down the driver or
motherboard. This is termed “Hot Swapping”.
Powered Driver and an Unpowered Receiver
Damage Risk
Hot swapping presents a potential risk to an unpowered or
powered down ECL device receiver and driver in either the
Negative or Positive mode when driven by a typical signal
level.
When a receiver PECL receiver V
CC
is off or powered
down, the V
CC
Power Supply typically appears as a low
impedance source at 0.0 V capable of sinking considerable
current. Typical driver signal levels present voltages that
forward bias the input ESD protection diode structure and
the input base collector junction. Potentially lethal current
paths may develop through forwarded junctions to V
CC
.
There is also a risk for a powered down or off NECL or
LVNECL receiver and driver. A V
EE
supply will typically
appear as a low impedance path to 0.0 V (GND). Typical
negative levels present signal voltages that will forward bias
the input ESD protection diode structure and the input base
collector junction to this low impedance path. Potentially
lethal current paths may develop through the forwarded
junctions and V
EE
to 0.0 V.
Powered down receiver risk may be managed in several
ways.
1. Physical Sequencing the supplies for V
EE
(Ground) and V
CC
(Power) may be physically
connected prior to signal lines by altering the
daughter board edge connection geometry, making
V
EE
and V
CC
connectors protrude and engage or
sequence first. V
EE
connectors could even be
sequenced prior to V
CC
.
This insures the supplies
are powered prior to input signal voltages.
2. Switching a relay (or analog switch) could be
used to open or close the supply lines insuring the
power supply line is opened when powered off.
3. Cap Coupling DC isolation of potentially
damaging current.
4. Series R an additional series impedance matching
resistor, R
S
, will act as power splitter with an
existing parallel termination resistor, R
T
, to
accomplish some current limiting to help manage
the risk. This will also attenuate the amplitude
50%, easily tolerated by most high gain, high input
sensitivity devices.
Using V
BB
Pin for V
BIAS
Some devices provide a convenient V
BB
pin for use as a
VBIAS reference supply to rebias a DC level. A DC rebias
level must be at the common mode voltage of the input
signal to properly preserve a 50% output duty cycle (see
AND8066). A package V
BB
pin may provide an internally
generated DC switching reference voltage for the device
inputs, and is available only to the package input pins. Do not
port one package V
BB
pin directly to another device without
current amplification. When used, decouple V
BB
to V
CC
(or
V
TT
) via a 0.01 to 0.001
F capacitor to suppress noise
injection. Limit current to less than 0.5 mA (Absolute
Maximum Rating source or sink) as shown in Figure 21.
When not used, V
BB
should be left open.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AND8020D | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| ANP-C-115 | JT 79C 79#22D PIN RECP |
| ANPC-185 | GPS Antenna for Automotive Aftermarket Applications |
| AO3400 | N-Channel Enhancement Mode Field Effect Transistor |
| AO3400L | N-Channel Enhancement Mode Field Effect Transistor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AND8020D | 制造商:AD 制造商全稱:Analog Devices 功能描述:Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| AND8028 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Precision Sub-One Volt 1.7 Ampere Output LDO |
| AND8028D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Precision Sub-One Volt 1.7 Ampere Output LDO |
| AND8031 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Isolated Precision Regulation of a Single 1.8 Volt Output from a Universal Line Input |
| AND8031D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Isolated Precision Regulation of a Single 1.8 Volt Output from a Universal Line Input |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。