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參數(shù)資料
| 型號： | AN8539SH |
| 廠商： | PANASONIC CORP |
| 元件分類： | XO, clock |
| 英文描述： | 300 MHz-band single PLL IC |
| 中文描述： | PHASE LOCKED LOOP, 300 MHz, PDSO10 |
| 封裝： | 0.225 INCH, PLASTIC, SSOP-10 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 54K |
| 代理商： | AN8539SH |
ICs for Mobile Communication
AN8539SH
5
I
Application Notes (continued)
1. Input level characteristics (continued)
2) REF input level characteristics
Input frequency (MHz)
I
30
20
10
0
10
20
0
5
10
15
20
25
30
T
a
=
85
°
C
T
a
=
30
°
C, 25
°
C, 85
°
C
T
a
=
25
°
C
V
CC
=
2.55 V to 3.3V
T
a
=
30
°
C
Upper limit
Lower limit
2. Characteristics specification
1) IF select specification
SELECT pin control enables you to switch IF as below:
SELECT
=
low
→
f
OUT
=
129.55 MHz, f
R
=
50 kHz (P
=
16, N
=
161, A
=
15, R
=
256)
SELECT
=
high
→
f
OUT
=
178 MHz, f
R
=
400 kHz (P
=
16, N
=
27, A
=
13, R
=
32)
2) Unlock detection and LD output specification
LD output is high in a lock mode and low in an unlock mode. Lock signal is outputted in a power save mode.
SELECT
=
high:Detection time is 2.6
μ
s. About detection accuracy, when a dividing output shifts
by
±
(78
×
3) ns for f
REF
=
400 kHz, it generates an unlock output.
SELECT
=
low :Detection time is 20
μ
s. About detection accuracy, when a dividing output shifts
by
±
(78
×
3) ns for f
REF
=
50 kHz, it generates an unlock output.
3) Power save control specification
When power save control pin (PS) is high, it is set to an operating mode. When it is low, it is set to power save mode.
4) Analog SW control specification
CPSUB is controlled by SW pin.
SW
=
low : CPSUB open
SW
=
high: CPSUB operation
5) Other specification
Set CMOS input pins, such as PS pin, SW pin, SELECT pin, etc., normally to V
CC
or GND.
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