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| 型號(hào)： | AN202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Testing and specifying FAST logic |
| 中文描述： | 快速測(cè)試，并指定邏輯 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大小： | 72K |
| 代理商： | AN202 |
Philips Semiconductors
Application note
AN202
Testing and specifying FAST logic
June 1987
4
a.
Board Layout
b.
Schematic
C1
J2
(OUTPUT ONLY)
DUT
R1
450
50
SCOPE
R2
500
J3 (3-STATE)
7V
J1 (INPUT ONLY)
R3
50
PULSE
GENERATOR
S1
V
S
1
V
S
2
V
S
3
V
T
(7V)
J1
(OUTPUT ONLY)
J1 (INPUT ONLY)
50pF C1
50
R3
500
R2
DEVICE PIN
R1
450
BOTTOM
SIDE
PAD
(BOTH SIDES)
TOP SIDE
GROUND
SF01269
Figure 2. FAST AC Test Fixture
HIGH-FREQUENCY DESIGN
The exact jig delay time is determined by the size of the universal jig
that is being used. It is important to know that the frequency
response of the jig must be High to prevent any delay factor from
varying with the edge rates. The frequency response of the jig
indicates how constant the impedance remains over frequency. The
characteristics impedance of a transmission line is expressed as:
Z
O
V
I
L
O
C
O
Where L
O
is the inductance per unit length, C
O
is the capacitance
per unit length, Z
O
is in Ohms, L
O
in Henrys, and C
O
in Farads.
Propagation velocity and its inverse, delay per unit length d, are also
expressed in L
O
and C
O
…
V
1
L
O
C
O
L
O
C
O
where
δ
is expressed in nanoseconds, L
O
is in microhenrys per unit
length, and C
O
in microfarads per unit length. From this, it is clear
that if the Z
O
changes over frequency, then the delay per unit length
will vary as well. Therefore, it is imperative to know how the jig
responds over frequency and that all measurement line lengths are
identical.
Frequency response also depends on the phase as well as the
magnitude of the impedance. If the phase changes so does the
delay, since delay is the derivative of phase change with frequency.
An S-parameter analysis is needed in evaluating jig performance.
UNIVERSAL JIG CONSTRUCTION
Jig universality is with respect to chip pin count and V
CC
and ground
pin placements and as such, separate universal test jigs are built for
14, 16, 20, 24, and 28 pin parts.
An S-parameter analysis was performed in a network analyzer to
optimize the jig layout. This assured that the jig had a flat frequency
response over the spectrum of interest for FAST products. Figure 2b
shows the schematic of the fixture and Figure 2a shows a drawing
of the board layout, component placement and signal paths. The
equipment used to analyze the jigs and loads was: HP8505A
Network Analyzer, HP8503A S-Parameter Test Set and HP8501A
Storage Normalizer. In some measurements the equipment was
driven by an HP9845B desk-top computer.
Jigs produced in this way should have minimal lead length to reduce
the characteristic inductance. This in turn minimizes reflections with
their accompanying waveform distortions. and measurement
inaccuracies.
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