參數(shù)資料
型號(hào)： AMIS49587C5872G
廠商： ON Semiconductor
文件頁數(shù)： 32/55頁
文件大?。?/td> 0K
描述： IC MODEM PLC 50/60MHZ 52QFN
標(biāo)準(zhǔn)包裝： 37
波特率： 可選
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 52-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-QFN（8x8）
包裝： 管件
AMIS49587
http://onsemi.com
38
7.3.2 WriteConfig_Request
AMIS4958x
Command
Interpreter
External CPU
WriteConfigNew_Request(0x71)
[Config data OK&& Command allowed&& !Test mode]
WriteConfigNew_Confirm(0x72)
[Config data error| Command not allowed| Test mode]
WriteConfigNew_Error (0x73)
On success,
mode is changed
to Master, Slave
or Spy
Figure 32. Sequence Diagram for WriteConfig_Request
Command can be issued at any time (If the status message allows it to be send) and will bring the MODEM in a ‘SET’ state
if the configuration data is correct. Depending on the configuration data, the final state of the MODEM will be Master, Slave
or Monitor.
<STX>
0x26 (Length)
0x71 (WriteConfig_Request)
Data_Config
CHK
With Data_Config, 36 bytes of configuration data as laid out in Tables 41 and 43.
Table 41. CONFIGURATION PARAMETERS
Field
Length
Value
Description
First Initiator MAC Address (FIMA)
2 bytes
0001 to 0FFF
Slave: First value for Initiator MAC address
XXXX
Master & Monitor: don’t care
Last Initiator MAC Address (LIMA)
2 bytes
0001 to 0FFF
Slave: Last value for Initiator MAC address
XXXX
Master & Monitor: don’t care
Local MAC Address
2 bytes
0FFE or
Slave Mode: New
0001 to (FIMA1)
FIMA to LIMA
Slave (Registered)
Master
XXXX
Monitor
Active Initiator Address
2 bytes
0000
Master, Slave (unlocked)
FIMA to LIMA
Slave (locked on an initiator)
XXXX
Monitor
Timeoutsynchroconfirm
2 bytes
0000 to FFFF
Slave: In seconds. (Not used in Master mode)
Timeoutframenotok
2 bytes
0000 to FFFF
Slave: In seconds (Not used in Master mode)
Timeoutnotaddressed
2 bytes
0000 to FFFF
Slave: In minutes (Not used in Master & Monitor mode)
XXXX
Monitor: Don’t care
Macgroupaddresses
10 bytes
0000 to 0FFF
Slave: 5 MAC group addresses (Not used in Master
mode)
Fs
2 bytes
0000 to FFFF
Step Register for the Space Frequency Fs
Fm
2 bytes
0000 to FFFF
Step Register for the Mark Frequency Fm
R_ZC_ADJUST
1 byte
00 to FF
Value according to the voltage level of the 50 Hz
information for the input of the PLL.
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