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參數(shù)資料
| 型號(hào)： | AM79C32A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | 數(shù)字用戶控制器⑩法（DSC⑩）電路 |
| 文件頁(yè)數(shù)： | 46/101頁(yè) |
| 文件大?。?/td> | 1607K |
| 代理商： | AM79C32A |
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46
Am79C30A/32A Data Sheet
D-Channel Status Register 2 — (DSR2) — Read Only
DSR2 has the format illustrated in Table 46.
Note:
*Following RESET, the Transmit buffer Available (bit 4) is set, producing a default value of 10H.
The DSR2 bits generate interrupts and are set/reset under the conditions shown in Table 47 (in addition to a hard-
ware reset or Idle mode).
Table 47.
DSR2 Interrupts
Table 46.
D-Channel Status Register 2
Bit
Logical 1
Logical 0 (Default Value)
0
Last byte of received packet
Not last byte of received packet
1
Receive byte available
Receive byte not available
2
Receive packet lost
Receive packet not lost
3
Last byte transmitted
Last byte not transmitted
4
Transmit buffer available
Transmit buffer not available*
5
Mark idle detected (15 or more contiguous 1s)
Mark idle not detected
6
Flag idle detected (more than two contiguous flags)
Flag idle not detected
7
Start of second received packet in FIFO
Second packet not yet in FIFO
Bit
Generate Interrupt
Bit Set
Bit Reset
0
Yes, if DMR3 bit 2 = 1 When last byte of a received packet is read from the
DCRB
When the microprocessor reads the
DSR2
1
Yes, if DMR1 bit 3 = 1 When DCRB contains one or more bytes of data
When DCRB is empty
2
Yes, if DMR3 bit 6 = 1 When two outstanding packets are received and not
serviced, and a third packet is received
When the microprocessor reads
DSR2
3
Yes, if DMR3 bit 4 = 1 When the last byte of a transmit packet is transferred from
the DCTB
When the microprocessor reads
DSR2
4
Yes, if DMR3 bit 5 = 1 When the DCTB is available to be loaded with a data byte When the DCTB is full
5
No
When 15 contiguous one bits have been detected in the
incoming D channel
When the first zero bit is detected
on the incoming D channel
6
No
When more than two contiguous flags are detected on the
incoming D channels, not including a closing flag
When a non-flag character is
detected on the incoming D channel
7
Yes, if EFCR bit 1 = 1 When start of second packet is in the receive FIFO
When second receive packet is not
present
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