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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 11/20/03
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
30049
Issue Date:
November 20, 2003
Rev:
A
Amendment/
+5
Am49PDL640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and
16 Mbit (1 M x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 2.7 to 3.1 volt
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High performance
— Access time as fast as 70 ns initial/ 25 ns subsequent
Package
— 73-Ball FBGA
Operating Temperature
— –25°C to +85°C
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Flash Memory Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
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Flex Bank
architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Bank A: 8 Mbit (4 Kw x 8 and 32Kw x 15)
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— Bank B: 24 Mbit (32 Kw x 48)
— Bank C: 24 Mbit (32 Kw x 48)
— Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
Manufactured on 0.17 μm process technology
SecSi (Secured Silicon) Sector: Extra 256 Byte sector
— Factory locked and identifiable:16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
— Customer lockable: Sector is one-time programmable. Once
sector is locked, data cannot be changed.
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
Boot sectors
— Top and bottom boot sectors in the same device
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
— Access time as fast as 70 ns
— Program time: 4 μs/word typical utilizing Accelerate function
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Ultra low power consumption (typical values)
— 23 mA active read current
— 15 mA program/erase current
— 200 nA in standby or automatic sleep mode
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Minimum 1 million write cycles guaranteed per sector
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20 year data retention at 125
°
C
— Reliable operation for the life of the system
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
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CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
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Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
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Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
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Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
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— Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
Pseudo SRAM Features
Power dissipation
— Operating: 30 mA maximum
— Standby: 100 μA maximum
— Deep Power-down current: 10 μA
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CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 2.7 to 3.1 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
Multiple pSRAM vendors available
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