參數(shù)資料
型號(hào)： AM49PDL129AH70IT
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁數(shù)： 15/82頁
文件大?。?/td> 565K
代理商： AM49PDL129AH70IT
December 18, 2003
Am49PDL127AH/Am49PDL129AH
13
A D V A N C E I N F O R M A T I O N
Table 1.
Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, A
IN
=
Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
Do not apply CE#f1 or 2 = V
IL
, CE#1ps = V
IL
and CE2ps = V
IH
at
the same time.
Don’t care or open LB#s or UB#s.
If WP#/ACC = V
IL
, the boot sectors will be protected. If WP#/ACC
= V
IH
the boot sectors protection will be removed.
If WP#/ACC = V
ACC
(9V), the program time will be reduced by
40%.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
If WP#/ACC = V
IL
, the two outermost boot sectors remain
protected. If WP#/ACC = V
IH
, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V
HH,
all sectors will
be unprotected.
Data will be retained in pSRAM.
Data will be lost in pSRAM.
2.
3.
4.
5.
6.
7.
8.
9.
Both CE#f1 inputs may be held low for this operation.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the OE# and appropriate CE#f1/CE#f2 (PDL129
only) pins to V
IL
. CE#f1 and CE#f2 are the power con-
trol and for PDL129 select the lower (CE#f1) or upper
(CE#f2) halves of the device. OE# is the output control
and gates array data to the output pins. WE# should
remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Operation
(Notes 1, 2)
CE#f1
Active
CE#f2
(PDL129
only)
CE#1ps CE2ps OE#
WE#
Addr.
LB#s
(Note
3)
UB#s
(Note
3)
RESET#
WP#/
ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from
Active Flash
(Note 7)
L (H)
H (L)
H
H
L
H
A
IN
X
X
H
L/H
D
OUT
D
OUT
(Note 8)
H
L
Write to Active
Flash
(Note 7)
L (H)
H (L)
H
H
H
L
A
IN
X
X
H
(Note 4)
D
IN
D
IN
(Note 8)
H
L
Standby
V
CC
±
0.3 V
H
H
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
Deep Power-down
Standby
V
CC
±
0.3 V
H
L
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
Output Disable (Note 9)
L (H)
H (L)
L
H
H
H
X
X
X
H
L/H
High-Z
High-Z
H
H
X
X
X
Flash Hardware
Reset
(Note 7)
X
H
H
X
X
X
X
X
L
L/H
High-Z
High-Z
(Note 8)
H
L
Sector Protect
(Notes 6, 10)
(Note 7)
L (H)
H (L)
H
H
H
L
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
D
IN
X
(Note 9)
H
L
Sector
Unprotect
(Notes 5, 9)
(Note 7)
L (H)
H (L)
H
H
H
L
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
V
ID
(Note 6)
D
IN
X
(Note 8)
H
L
Temporary
Sector
Unprotect
(Note 7)
X
H
H
X
X
X
X
X
V
ID
(Note 6)
D
IN
High-Z
(Note 8)
H
L
Read from pSRAM
H
H
L
H
L
H
A
IN
L
L
H
X
D
OUT
D
OUT
H
L
High-Z
D
OUT
L
H
D
OUT
High-Z
Write to pSRAM
H
H
L
H
X
L
A
IN
L
L
H
X
D
IN
D
IN
H
L
High-Z
D
IN
L
H
D
IN
High-Z
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