參數(shù)資料
型號(hào)： AM49PDL129AH61IT
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁數(shù)： 77/82頁
文件大小： 565K
代理商： AM49PDL129AH61IT
December 18, 2003
Am49PDL127AH/Am49PDL129AH
75
A D V A N C E I N F O R M A T I O N
PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of
write to the end of write.
Figure 28.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
61
70
t
WC
Write Cycle Time
Min
55
70
ns
t
Cw
Chip Enable to End of Write
Min
50
55
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
50
55
ns
t
BW
UB#s, LB#s to End of Write
Min
50
55
ns
t
WP
Write Pulse Time
Min
50
55
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Max
25
ns
t
DW
Data to Write Time Overlap
Min
25
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
Min
5
ns
Address
CE1#s
Data Undefined
WE#
Data In
Data Out
t
WC
t
CW
(See Note 1)
t
AW
High-Z
High-Z
Data Valid
CE2s
t
CW
(See Note 1)
t
WP
(See Note 4)
t
(See Note 3)
t
WR
t
DW
t
DH
t
OW
t
WHZ
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