參數(shù)資料
型號: AM49PDL129AH61IS
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁數(shù): 8/82頁
文件大?。?/td> 565K
代理商: AM49PDL129AH61IS
6
Am49PDL127AH/Am49PDL129AH
December 18, 2003
A D V A N C E I N F O R M A T I O N
Between Pseudo SRAM and Flash................................................. 59
Flash AC Characteristics . . . . . . . . . . . . . . . . . . .60
Read-Only Operations – Am29PDL127H ...............................60
Read-Only Operations – Am29PDL129H ...............................60
Figure 13. Read Operation Timings................................................ 61
Figure 14. Page Read Operation Timings....................................... 61
Hardware Reset (RESET#) ....................................................62
Figure 15. Reset Timings................................................................ 62
Erase and Program Operations ..............................................63
Figure 16. Program Operation Timings........................................... 64
Figure 17. Accelerated Program Timing Diagram........................... 64
Figure 18. Chip/Sector Erase Operation Timings ........................... 65
Figure 19. Back-to-back Read/Write Cycle Timings ....................... 66
Figure 20. Data# Polling Timings (During Embedded Algorithms).. 66
Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 67
Figure 22. DQ2 vs. DQ6.................................................................. 67
Temporary Sector Unprotect ..................................................68
Figure 23. Temporary Sector Unprotect Timing Diagram............... 68
Figure 24. Sector/Sector Block Protect and
Unprotect Timing Diagram.............................................................. 69
Alternate CE#f1 Controlled Erase and Program Operations ..70
Figure 25. Flash Alternate CE#f1 Controlled Write (Erase/Program)
Operation Timings.......................................................................... 71
Pseudo SRAM AC Characteristics . . . . . . . . . . . 72
Power Up Time .......................................................................72
Read Cycle .............................................................................72
Figure 26. Pseudo SRAM Read Cycle—Address Controlled......... 72
Figure 27. Pseudo SRAM Read Cycle........................................... 73
Write Cycle .............................................................................74
Figure 28. Pseudo SRAM Write Cycle—WE# Control................... 74
Figure 29. Pseudo SRAM Write Cycle—CE1#s Control................ 75
Figure 30. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 76
Erase And Programming Performance . . . . . . . 77
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 77
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 77
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 77
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 78
TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............78
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 79
相關PDF資料
PDF描述
AM49PDL127AH 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH61IS 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH61IT 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH70IS 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH70IT 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
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