參數(shù)資料
型號： AM49PDL127AH
廠商： Spansion Inc.
英文描述： 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
中文描述： 128兆位（8米× 16位），3.0伏的CMOS只，同時作業(yè)閃存和16兆位（1米× 16位）的CMOS偽靜態(tài)隨機存儲器
文件頁數(shù)： 43/82頁
文件大?。?/td> 565K
代理商： AM49PDL127AH
December 18, 2003
Am49PDL127AH/Am49PDL129AH
41
A D V A N C E I N F O R M A T I O N
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region com-
mand sequence to return to reading and writing the
remainder of the array.
The SecSi Sector lock must be used with caution
since, once locked, there is no procedure available for
unlocking the SecSi Sector area and none of the bits
in the SecSi Sector memory space can be modified in
any way.
SecSi Sector Protection Bits
The SecSi Sector Protection Bits prevent program-
ming of the SecSi Sector memory area. Once set, the
SecSi Sector memory area contents are non-modifi-
able.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The
system must provide the proper signals to the control
pins to prevent unintentional writes when V
CC
is
greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#,
CE#f1, CE#f2 or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE#f1 =CE#f2 = V
IH
or WE# = V
IH
. To initiate a
write cycle, CE#f1/CE#f2 and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE#f1 = V
IL
and OE# = V
IH
during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 12–15. To terminate reading CFI data,
the system must write the reset command. The CFI
Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase al-
gorithm.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 12–15. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
Table 12.
CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
相關PDF資料
PDF描述
AM49PDL127AH61IS 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH61IT 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH70IS 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH70IT 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL129AH 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
相關代理商/技術參數(shù)
參數(shù)描述
AM49PDL127AH61IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH61IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127AH70IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
AM49PDL127BH 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
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