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參數(shù)資料
| 型號(hào)： | AM49LV128BML15NS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 12 X 9 MM, FBGA-64 |
| 文件頁(yè)數(shù)： | 62/98頁(yè) |
| 文件大?。?/td> | 1016K |
| 代理商： | AM49LV128BML15NS |
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60
Am49LV128BM
June 17, 2004
PSRAM AC CHARACTERISTICS
Write Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low
without any address change.
2. Minimum value must be equal or greater than the sum of
write pulse (t
CW
, T
WP
, T
BW
) and write recovery time (t
WCR
,
T
WR
or t
BR
).
3. Write pulse is defined from High to Low transition of CE1#,
WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is
defined to the High to Low transition of CE1# or WE#
whichever occurs last.
5. Applicable for byte mask only. Byte mask hold time is
defined from the Low to High transition of CE1# or WE#
whichever occurs first.
6. Write recovery is defined from Low to High transition of
CE1#, WE#, or LB#/UB#, whichever occurs first.
7. If OE# is Low after minimum t
OHCL
, read cycle is initiated. In
other words, OE# must be brought to High within 5 ns after
CE1# is brought to Low. Once read cycle is initiated, new
write pulse should be input after minimum t
RC
is met
8. If OE# is Low after new address input, read cycle is
initiated. In other words, OE# must be brought to High at
the same time or before new address valid. Once read
cycle is initiated, new write pulse should be input after
minimum t
RC
is met and data bus is in High-Z
9. Absolute minimum values and defined at minimum V
IH
level.
10. If the actual value of t
WHOL
is shorter than the specified
minimum values, the actual t
AA
of following Read may
become longer by the amount of subtracting the actual
value from the specified minimum value.
Parameter
Symbol
t
WC
t
AS
t
CW
t
WP
t
BW
t
BS
t
BH
t
WRC
t
WR
t
BR
t
DS
t
DH
t
OHCL
t
OES
t
WHOL
t
BWO
t
CP
t
AH
Value
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
ns
ns
Min.
65
0
40
40
40
-5
-5
12
7.5
12
12
0
-5
0
12
30
12
0
Max.
1000
–
–
–
–
–
–
–
1000
1000
–
–
–
–
–
–
–
–
Write Cycle Time (Notes 1, 2)
Address Setup Time (Note 3)
CE1# Write Pulse Width (Note 3)
WE# Write Pulse Width (Note 3)
LB#/UB# Write Pulse Width (Note 3)
LB#/UB# Byte Mask Setup Time (Note 4)
LB#/UB# Byte Mask Hold Time (Note 5)
CE1# Write Recovery Time (Note 6)
WE# Write Recovery Time (Note 6)
LB#/UB# Write Recovery Time (Note 6)
Data Setup Time
Data Hold Time
OE# High to CE1# Low Setup Time for Write (Note 7)
OE# High to Address Setup Time for Write (Note 8)
WE#/UB#/LB# High to OE# Low Setup Time for Read (Note 10)
LB# and UB# Write Pulse Overlap
CE1# High Pulse Width
Address Hold Time for Write End (Note 3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM49LV128BML15NT | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
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| AM49LV6408MB10IT | Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM49LV128BML15NT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV4608M | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM |
| AM49LV4608MB10IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM |
| AM49LV4608MB10IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM |
| AM49LV4608MB11IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM |
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