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參數(shù)資料
| 型號： | AM49LV128BMAH11NT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 12 X 9 MM, FBGA-64 |
| 文件頁數(shù)： | 88/98頁 |
| 文件大?。?/td> | 1016K |
| 代理商： | AM49LV128BMAH11NT |
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86
Am49LV128BM
June 17, 2004
TIMING WAVEFORM OF PAGE MODE WRITE CYCLE
POWER SAVINGS MODES
The PSRAM has three power savings modes:
Reduced Memory Size
Partial Array Refresh
Deep Sleep Mode
The operation of the power saving modes is controlled
by setting the Variable Address Register (VAR). This
VAR is used to enable/disable the various low power
modes.
The VAR is set by using the timings. The register must
be set in less then 1μs after ZZ# is enabled low.
Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be
operated as a 8Mb, 16Mb or a 24Mb device. The
mode and array size are determined by the settings in
the VA register. The VA register is set according to the
timings and the bit settings. The RMS mode is enabled
at the time of ZZ# transitioning high and the mode re-
mains active until the register is updated. To return to
the full 32Mb address space, the VA register must be
reset using the previously defined procedures.
Partial Array Refresh (PAR)
In this mode, the internal refresh operation can be re-
stricted to a 8Mb, 16Mb or 24Mb portion of the array.
The mode and array partition to be refreshed are de-
termined by the settings in the VAR register. The VAR
register is set according to the timings and the bit set-
tings. In this mode, when ZZ# is taken low, only the
portion of the array that is set in the register is re-
freshed. The operating mode is only available during
standby time and once ZZ# is returned high, the de-
vice resumes full array refresh. All future PAR cycles
will use the contents of the VA register. To change the
address space of the PAR mode, the VA register must
be reset using the previously defined procedures.
The default state for the ZZ# register will be such that
ZZ# low will put the device into PAR mode after 1μs
and never initiate a deep sleep mode unless appropri-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM49LV128BMAH15NS | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAH15NT | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAL11NS | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAL11NT | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAL15NS | 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM49LV128BMAH15NS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAH15NT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAL11NS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAL11NT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
| AM49LV128BMAL15NS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) |
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