參數(shù)資料
型號(hào)： AM49DL6408H85IT
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, LEAD FREE, PLASTIC, FBGA-73
文件頁(yè)數(shù)： 5/57頁(yè)
文件大?。?/td> 426K
代理商： AM49DL6408H85IT
March 12, 2004
Am49DL6408H
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 4
Flash memory Block Diagram . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions ....................................6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
MCP Device Bus Operations . . . . . . . . . . . . . . . . .8
Requirements for Reading Array Data ...................................10
Writing Commands/Command Sequences ............................10
Accelerated ProgramOperation ..........................................10
Autoselect Functions ...........................................................10
Simultaneous Read/Write Operations with Zero Latency .......10
Automatic Sleep Mode ...........................................................11
RESET#: Hardware Reset Pin ...............................................11
Output Disable Mode ..............................................................11
Table 2. Am29DL640H Sector Architecture ....................................11
Table 3. Bank Address ....................................................................14
Table 4. SecSi
Sector Addresses ...............................................14
Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................15
Write Protect (WP#) ................................................................16
Table 6. WP#/ACC Modes ..............................................................16
Temporary Sector Unprotect ..................................................16
Figure 1. Temporary Sector Unprotect Operation........................... 16
Figure 2. In-SystemSector Protect/Unprotect Algorithms.............. 17
SecSi (Secured Silicon) Sector
FlashMemoryRegion ............................................................18
Figure 3. SecSi Sector Protect Verify.............................................. 19
Hardware Data Protection ......................................................19
Low V
CC
Write Inhibit ...........................................................19
Write Pulse “Glitch” Protection ............................................19
Logical Inhibit ......................................................................19
Power-Up Write Inhibit .........................................................19
Common Flash Memory Interface (CFI) . . . . . . .19
Flash Command Definitions . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................23
Reset Command .....................................................................23
Autoselect Command Sequence ............................................23
Enter SecSi Sector/Exit SecSi Sector
Command Sequence ..............................................................23
Word ProgramCommand Sequence .....................................24
Unlock Bypass Command Sequence ..................................24
Figure 4. ProgramOperation.......................................................... 25
Chip Erase Command Sequence ...........................................25
Sector Erase Command Sequence ........................................25
Erase Suspend/Erase Resume Commands ...........................26
Figure 5. Erase Operation............................................................... 26
Flash Write Operation Status . . . . . . . . . . . . . . . .28
DQ7: Data#Polling .................................................................28
Figure 6. Data#Polling Algorithm................................................... 28
DQ6: Toggle Bit I ....................................................................29
Figure 7. Toggle Bit Algorithm........................................................ 29
DQ2: Toggle Bit II ...................................................................30
Reading Toggle Bits DQ6/DQ2 ...............................................30
DQ5: Exceeded Timng Limts ................................................30
DQ3: Sector Erase Timer .......................................................30
Table 12. Write Operation Status ...................................................31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Figure 8. MaximumNegative OvershootWaveform...................... 32
Figure 9. MaximumPositive OvershootWaveform........................ 32
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33
CMOS Compatible ..................................................................33
Figure 10. I
CC1
Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 34
Figure 11. Typical I
vs. Frequency............................................ 34
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup.................................................................... 36
Figure 13. Input Waveforms and Measurement Levels................. 36
Figure 14. ...................................................................................... 36
Read-Only Operations ...........................................................37
Figure 15. Read Operation Timngs............................................... 37
Hardware Reset (RESET#) ....................................................38
Figure 16. Reset Timngs............................................................... 38
Erase and ProgramOperations ..............................................39
Figure 17. ProgramOperation Timngs.......................................... 40
Figure 18. Accelerated ProgramTimng Diagram.......................... 40
Figure 19. Chip/Sector Erase Operation Timngs.......................... 41
Figure 20. Back-to-back Read/Write Cycle Timngs...................... 42
Figure 21. Data# Polling Timngs (During Embedded Algorithms). 42
Figure 22. Toggle Bit Timngs (During Embedded Algorithms)...... 43
Figure 23. DQ2 vs. DQ6................................................................. 43
Temporary Sector Unprotect ..................................................44
Figure 24. Temporary Sector Unprotect Timng Diagram.............. 44
Figure 25. Sector/Sector Block Protect and
Unprotect Timng Diagram............................................................. 45
Alternate CE#f Controlled Erase and ProgramOperations ....46
Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)
OperationTimngs.......................................................................... 47
Pseudo SRAM AC Characteristics . . . . . . . . . . . 48
Power Up Time .......................................................................48
Read Cycle .............................................................................48
Figure 27. Pseudo SRAMRead Cycle—Address Controlled......... 48
Figure 28. Pseudo SRAMRead Cycle........................................... 49
Write Cycle .............................................................................50
Figure 29. Pseudo SRAMWrite Cycle—WE#Control................... 50
Figure 30. Pseudo SRAMWrite Cycle—CE1#s Control................ 51
Figure 31. Pseudo SRAMWrite Cycle—
UB#s and LB#s Control.................................................................. 52
Flash Erase And Programming Performance . . 53
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 53
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 53
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54
FLJ073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm..............54
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
相關(guān)PDF資料
PDF描述
AM49DL640AH 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
AM49DL640AH56IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
AM49DL640AH56IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
AM49DL640AH70IS 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
AM49DL640AH70IT 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
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