參數資料
型號： AM49DL320BGB85IS
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM的32兆位（4個M × 8位/ 2米x 16位），3.0伏的CMOS只，同時
文件頁數： 4/64頁
文件大?。?/td> 569K
代理商： AM49DL320BGB85IS
June 25, 2002
Am49DL320BG
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions ....................................7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Valid Combinations ................................................................9
MCP Device Bus Operations . . . . . . . . . . . . . . . .10
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
... 10
Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
..... 11
Word/Byte Configuration ........................................................12
Requirements for Reading Array Data ...................................12
Writing Commands/Command Sequences ............................12
Accelerated ProgramOperation ..........................................12
Autoselect Functions ...........................................................12
Simultaneous Read/Write Operations with Zero Latency .......12
Standby Mode ........................................................................13
Automatic Sleep Mode ...........................................................13
RESET#: Hardware Reset Pin ...............................................13
Output Disable Mode ..............................................................13
Table 3. Top Boot Sector Adresses ................................................14
Top Boot SecSi
Sector Addresses............................................. 15
Table 5. BottomBoot Sector Addresses .........................................16
BottomBoot SecSi
Sector Addresses........................................ 17
Autoselect Mode .....................................................................18
Sector/Sector Block Protection and Unprotection ..................18
Table 7. Top Boot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................18
Table 8. BottomBoot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................19
Write Protect (WP#) ................................................................19
Temporary Sector/Sector Block Unprotect .............................19
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-SystemSector/Sector Block Protect and Unprotect Algo-
rithms.............................................................................................. 21
SecSi (Secured Silicon) Sector Flash Memory Region ..........22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory ..........................................................................22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................22
Hardware Data Protection ......................................................22
Low V
CC
Write Inhibit ...........................................................22
Write Pulse
“
Glitch
”
Protection ............................................22
Logical Inhibit ......................................................................22
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 9. CFI Query Identification String.......................................... 23
SystemInterface String................................................................... 24
Table 11. Device Geometry Definition............................................ 24
Table 12. Primary Vendor-Specific Extended Query...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . .26
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..26
Byte/Word ProgramCommand Sequence .............................27
Unlock Bypass Command Sequence ..................................27
Figure 3. ProgramOperation.......................................................... 28
Chip Erase Command Sequence ...........................................28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ...........................29
Figure 4. Erase Operation.............................................................. 29
Table 13. Command Definitions (Flash Word Mode)...................... 30
Table 14. Command Definitions (Flash Byte Mode)....................... 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data#Polling .................................................................32
Figure 5. Data#Polling Algorithm.................................................. 32
RY/BY#: Ready/Busy#............................................................33
DQ6: Toggle Bit I ....................................................................33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ...................................................................34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timng Limts ................................................34
DQ3: Sector Erase Timer .......................................................34
Table 15. Write Operation Status ...................................................35
Industrial (I) Devices ............................................................36
V
CC
f/V
CC
s Supply Voltage ...................................................36
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ..................................................................37
Figure 9. I
CC1
Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 39
Figure 10. Typical I
vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Figure 12. Input Waveforms and Measurement Levels................. 40
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41
CE#s Timng ...........................................................................41
Figure 13. Timng Diagramfor Alternating
Between Pseudo SRAM to Flash................................................... 41
Read-Only Operations ...........................................................42
Figure 14. Read Operation Timngs............................................... 42
Hardware Reset (RESET#) ....................................................43
Figure 15. Reset Timngs............................................................... 43
Word/Byte Configuration (CIOf) ..............................................44
Figure 16. CIOf Timngs for Read Operations................................ 44
Figure 17. CIOf Timngs for Write Operations................................ 44
Erase and ProgramOperations ..............................................45
Figure 18. ProgramOperation Timngs.......................................... 46
Figure 19. Accelerated ProgramTimng Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timngs.......................... 47
Figure 21. Back-to-back Read/Write Cycle Timngs...................... 48
Figure 22. Data# Polling Timngs (During Embedded Algorithms). 48
Figure 23. Toggle Bit Timngs (During Embedded Algorithms)...... 49
Figure 24. DQ2 vs. DQ6................................................................. 49
Temporary Sector Unprotect ..................................................50
Figure 25. Temporary Sector Unprotect Timng Diagram.............. 50
Figure 26. Sector/Sector Block Protect and
Unprotect Timng Diagram............................................................. 51
Alternate CE#f Controlled Erase and ProgramOperations ....52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
OperationTimngs.......................................................................... 53
Read Cycle .............................................................................54
Figure 28. Psuedo SRAMRead Cycle........................................... 54
Figure 29. Page Read Timng........................................................ 55
Write Cycle .............................................................................56
Figure 30. Pseudo SRAMWrite Cycle
—
WE#Control................... 56
Figure 31. Pseudo SRAMWrite Cycle
—
CE1#s Control................ 57
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